J. Semicond. > Volume 35 > Issue 9 > Article Number: 095008

An accurate RLGC circuit model for dual tapered TSV structure

Zhen Wei , , Xiaochun Li and Junfa Mao

+ Author Affiliations + Find other works by these authors

PDF

Abstract: A fast RLGC circuit model with analytical expression is proposed for the dual tapered through-silicon via (TSV) structure in three-dimensional integrated circuits under different slope angles at the wide frequency region. By describing the electrical characteristics of the dual tapered TSV structure, the RLGC parameters are extracted based on the numerical integration method. The RLGC model includes metal resistance, metal inductance, substrate resistance, outer inductance with skin effect and eddy effect taken into account. The proposed analytical model is verified to be nearly as accurate as the Q3D extractor but more efficient.

Key words: tapered TSVRLGC circuit modelnumerical integration methodcurrent continuityeddy effect

Abstract: A fast RLGC circuit model with analytical expression is proposed for the dual tapered through-silicon via (TSV) structure in three-dimensional integrated circuits under different slope angles at the wide frequency region. By describing the electrical characteristics of the dual tapered TSV structure, the RLGC parameters are extracted based on the numerical integration method. The RLGC model includes metal resistance, metal inductance, substrate resistance, outer inductance with skin effect and eddy effect taken into account. The proposed analytical model is verified to be nearly as accurate as the Q3D extractor but more efficient.

Key words: tapered TSVRLGC circuit modelnumerical integration methodcurrent continuityeddy effect



References:

[1]

Banerjee K, Souri S J, Kapur P. 3-D ICs:a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration[J]. Proc IEEE, 2001, 89: 602. doi: 10.1109/5.929647

[2]

Davis W R, Wilson J, Mick S. Demystifying 3D ICs:the pros and cons of going vertical[J]. Design and Test of Computers IEEE, 2005, 22: 498. doi: 10.1109/MDT.2005.136

[3]

Beica R, Siblerud P, Sharbono C. Advanced metallization for 3D integration[J]. Electronics Packaging Technology Conference, 2008(10): 212.

[4]

Yu G. Study of DRIE's application in through silicon via (TSV) technology. Su Zhou University, 2009

[5]

Leung L L W, Chen K J. Microwave characterization and modeling of high aspect ratio through-wafer interconnect vias in silicon substrates[J]. IEEE Trans Microw Theory Tech, 2005, 53: 2472. doi: 10.1109/TMTT.2005.852782

[6]

Savidis I, Friedman E G. Electrical modeling and characterization of 3-D vias[J]. IEEE International Symposium on Circuits and Systems, 2008: 784.

[7]

Savidis I, Friedman E G. Closed-form expressions of 3-D via resistance, inductance, and capacitance[J]. IEEE Trans Electron Devices, 2009, 56: 1873. doi: 10.1109/TED.2009.2026200

[8]

Katti G, Stucchi M, De Meyer K. Electrical modeling and characterization of through silicon via for three-dimensional ICs[J]. IEEE Trans Electron Devices, 2010, 57: 256. doi: 10.1109/TED.2009.2034508

[9]

Savidis I, Alam S M, Jain A. Electrical modeling and characterization of through-silicon vias (TSVs) for 3-D integrated circuits[J]. Microelectron J, 2010, 41: 9. doi: 10.1016/j.mejo.2009.10.006

[10]

Xu C, Li H, Suaya R. Compact AC modeling and performance analysis of through-silicon vias in 3-D ICs[J]. IEEE Trans Electron Devices, 2010, 57: 3405. doi: 10.1109/TED.2010.2076382

[11]

Wang F, Zhu Z, Yang Y. Capacitance characterization of tapered through-silicon-via considering MOS effect[J]. Microelectron J, 2013, 45(2): 205.

[12]

Liang Y, Li Y. Closed-form expressions for the resistance and the inductance of different profiles of through-silicon vias[J]. Electron Device Lett, 2011, 32(3): 393. doi: 10.1109/LED.2010.2099203

[13]

Li H, Banerjee K. High-frequency analysis of carbon nanotube interconnects and implications for on-chip inductor design[J]. IEEE Trans Electron Devices, 2009, 56: 2202. doi: 10.1109/TED.2009.2028395

[14]

Jones D S. The theory of electromagnetism. New York:Macmillan, 1964

[15]

Arfken G B, Weber H J, Ruby L. Mathematical methods for physicists. Vol. 6. New York:Academic Press, 1985

[16]

Abramowitz M, Stegun I A. Handbook of mathematical functions with formulas, graphs, and mathematical tables. National Bureau of Standards Applied Mathematics Series 55, Tenth Printing, 1972

[17]

Hayt W H, Buck J A. Engineering electromagnetics. New York, 2006

[1]

Banerjee K, Souri S J, Kapur P. 3-D ICs:a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration[J]. Proc IEEE, 2001, 89: 602. doi: 10.1109/5.929647

[2]

Davis W R, Wilson J, Mick S. Demystifying 3D ICs:the pros and cons of going vertical[J]. Design and Test of Computers IEEE, 2005, 22: 498. doi: 10.1109/MDT.2005.136

[3]

Beica R, Siblerud P, Sharbono C. Advanced metallization for 3D integration[J]. Electronics Packaging Technology Conference, 2008(10): 212.

[4]

Yu G. Study of DRIE's application in through silicon via (TSV) technology. Su Zhou University, 2009

[5]

Leung L L W, Chen K J. Microwave characterization and modeling of high aspect ratio through-wafer interconnect vias in silicon substrates[J]. IEEE Trans Microw Theory Tech, 2005, 53: 2472. doi: 10.1109/TMTT.2005.852782

[6]

Savidis I, Friedman E G. Electrical modeling and characterization of 3-D vias[J]. IEEE International Symposium on Circuits and Systems, 2008: 784.

[7]

Savidis I, Friedman E G. Closed-form expressions of 3-D via resistance, inductance, and capacitance[J]. IEEE Trans Electron Devices, 2009, 56: 1873. doi: 10.1109/TED.2009.2026200

[8]

Katti G, Stucchi M, De Meyer K. Electrical modeling and characterization of through silicon via for three-dimensional ICs[J]. IEEE Trans Electron Devices, 2010, 57: 256. doi: 10.1109/TED.2009.2034508

[9]

Savidis I, Alam S M, Jain A. Electrical modeling and characterization of through-silicon vias (TSVs) for 3-D integrated circuits[J]. Microelectron J, 2010, 41: 9. doi: 10.1016/j.mejo.2009.10.006

[10]

Xu C, Li H, Suaya R. Compact AC modeling and performance analysis of through-silicon vias in 3-D ICs[J]. IEEE Trans Electron Devices, 2010, 57: 3405. doi: 10.1109/TED.2010.2076382

[11]

Wang F, Zhu Z, Yang Y. Capacitance characterization of tapered through-silicon-via considering MOS effect[J]. Microelectron J, 2013, 45(2): 205.

[12]

Liang Y, Li Y. Closed-form expressions for the resistance and the inductance of different profiles of through-silicon vias[J]. Electron Device Lett, 2011, 32(3): 393. doi: 10.1109/LED.2010.2099203

[13]

Li H, Banerjee K. High-frequency analysis of carbon nanotube interconnects and implications for on-chip inductor design[J]. IEEE Trans Electron Devices, 2009, 56: 2202. doi: 10.1109/TED.2009.2028395

[14]

Jones D S. The theory of electromagnetism. New York:Macmillan, 1964

[15]

Arfken G B, Weber H J, Ruby L. Mathematical methods for physicists. Vol. 6. New York:Academic Press, 1985

[16]

Abramowitz M, Stegun I A. Handbook of mathematical functions with formulas, graphs, and mathematical tables. National Bureau of Standards Applied Mathematics Series 55, Tenth Printing, 1972

[17]

Hayt W H, Buck J A. Engineering electromagnetics. New York, 2006

[1]

Song Liu, Guangbao Shan, Chengmin Xie, Xinrong Du. A transmission line-type electrical model for tapered TSV considering MOS effect and frequency-dependent behavior. J. Semicond., 2015, 36(2): 024009. doi: 10.1088/1674-4926/36/2/024009

[2]

liang Tao, Jia Xinzhang. A numerical integration-based yield estimation method for integrated circuits. J. Semicond., 2011, 32(4): 045012. doi: 10.1088/1674-4926/32/4/045012

[3]

Zhu Yangjun, Miao Qinghai, Zhang Xinghua, Han Zhengsheng. A novel electrical measurement method of peak junction temperature based on the excessive thermotaxis effect of low current. J. Semicond., 2009, 30(9): 094005. doi: 10.1088/1674-4926/30/9/094005

[4]

Si Yujuan, Xu Yanlei, Lang Liuqi, Chen Xinfa, Liu Shiyong. A New AC Driving Method for a Current-Programmed AM-OLED Pixel Circuit. J. Semicond., 2006, 27(9): 1562.

[5]

Hari Shanker Gupta, A S Kiran Kumar, M. Shojaei Baghini, Subhananda Chakrabarti, Sanjeev Mehta, Arup Roy Chowdhury, Dinesh K Sharma. Design of current mirror integration ROIC for snapshot mode operation. J. Semicond., 2016, 37(10): 105001. doi: 10.1088/1674-4926/37/10/105001

[6]

Hu Huiyong, Zhang Heming, Dai Xianying, Xuan Rongxi, Cui Xiaoying, Wang Qing, Jiang Tao. Transport Current Model of SiGe HBT. J. Semicond., 2006, 27(6): 1059.

[7]

Deng Linfeng, Yu Yuehui, Peng Yabin, Zhou Yuming, Liang Lin, Wang Lu. Physical Model and Numerical Algorithm Realization for RSD. J. Semicond., 2007, 28(6): 931.

[8]

K. Bekhouche, N. Sengouga, B. K. Jones. Numerical simulation of the effect of gold doping on the resistance to neutron irradiation of silicon diodes. J. Semicond., 2015, 36(1): 014001. doi: 10.1088/1674-4926/36/1/014001

[9]

Wang Xiaodong, Wu Xuming, , Wang Qing, Cao Yulian, He Guorong. Numerical Analysis of the Effect of a DBR with Graded Interfaces on the Resonant Cavity of a VCSEL. J. Semicond., 2006, 27(11): 2011.

[10]

Wu Qisong, Yang Haigang, Yin Tao, Zhang Chong. A high precision CMOS weak current readout circuit. J. Semicond., 2009, 30(7): 075011. doi: 10.1088/1674-4926/30/7/075011

[11]

Chen Jinhuo, Hu Jiaxing, Zhu Yunlong. A novel method to analyze the contact resistance effect on OTFTs. J. Semicond., 2012, 33(12): 124005. doi: 10.1088/1674-4926/33/12/124005

[12]

Li Kun, Teng Jianfu, Xuan Xiuwei. Effect of collector bias current on the linearity of common-emitter BJT amplifiers. J. Semicond., 2010, 31(12): 124012. doi: 10.1088/1674-4926/31/12/124012

[13]

Miao Qinghai, Zhu Yangjun, Zhang Xinghua, Lu Shuojin. Excessive Thermotaxis Effect of Low Current in pn Junction and Theoretical Analog Calculation. J. Semicond., 2006, 27(9): 1595.

[14]

O.Ya Olikh, K.V. Voitenko, R.M. Burbelo, JaM. Olikh. Effect of ultrasound on reverse leakage current of silicon Schottky barrier structure. J. Semicond., 2016, 37(12): 122002. doi: 10.1088/1674-4926/37/12/122002

[15]

Han Lei, Wang Yujun, Zhang Xiaoxing, Dai Yujie, Lü Yingjie. A simple and effective method to achieve the successful start-up of a current reference. J. Semicond., 2012, 33(8): 085008. doi: 10.1088/1674-4926/33/8/085008

[16]

Zhang Lei, Yu Zhiping, He Xiangqing. A Statistical Method for Characterizing CMOS Process Fluctuations in Subthreshold Current Mirrors. J. Semicond., 2008, 29(1): 82.

[17]

Liu Ke, , Jian Hongyan, Huang Chenling, Tang Zhangwen. Suppressing of On-Chip Inductor Current Crowding by a Multi-Current-Path Method. J. Semicond., 2006, 27(9): 1690.

[18]

Liu Zhan, Gu Xiaofeng, Yu Zongguang, Hu Xiduo, Zang Jiafeng. A New Hydrodynamic Model Method for Semiconductor Device Simulation. J. Semicond., 2008, 29(8): 1570.

[19]

Cui Yuanshun. Quantum Circuit Equation and Quantum Current of Mesoscopic Electron Resonator with Charge Discreteness. J. Semicond., 2007, 28(10): 1580.

[20]

Guo Wei, Yang Xing, Zhu Dazhong. Design and research of an LED driving circuit with accurate proportional current sampling mode. J. Semicond., 2010, 31(4): 045008. doi: 10.1088/1674-4926/31/4/045008

Search

Advanced Search >>

GET CITATION

Z Wei, X C Li, J F Mao. An accurate RLGC circuit model for dual tapered TSV structure[J]. J. Semicond., 2014, 35(9): 095008. doi: 10.1088/1674-4926/35/9/095008.

Export: BibTex EndNote

Article Metrics

Article views: 808 Times PDF downloads: 9 Times Cited by: 0 Times

History

Manuscript received: 28 January 2014 Manuscript revised: 25 March 2014 Online: Published: 01 September 2014

Email This Article

User name:
Email:*请输入正确邮箱
Code:*验证码错误