J. Semicond. > Volume 35 > Issue 9 > Article Number: 095009

A 14-bit 100-MS/s CMOS pipelined ADC featuring 83.5-dB SFDR

Nan Zhao , , Qi Wei , Huazhong Yang and Hui Wang

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Abstract: This paper demonstrates a 14-bit 100 MS/s CMOS pipelined analog-to-digital converter (ADC). The nonlinearity model for bootstrapped switches is established to optimize the design parameters of bootstrapped switches, and the calculations based on this model agree well with the measurement results. In order to achieve high linearity, a gradient-mismatch cancelling technique is proposed, which eliminates the first order gradient error of sampling capacitors by combining arrangement of reference control signals and capacitor layout. Fabricated in a 0.18-μm CMOS technology, this ADC occupies 10.16-mm2 area. With statistics-based background calibration of finite opamp gain in the first stage, the ADC achieves 83.5-dB spurious free dynamic range and 63.7-dB signal-to-noise-and distortion ratio respectively, and consumes 393 mW power with a supply voltage of 2 V.

Key words: pipelined ADCbootstrapped switchgradient errorpseudo-random sequence

Abstract: This paper demonstrates a 14-bit 100 MS/s CMOS pipelined analog-to-digital converter (ADC). The nonlinearity model for bootstrapped switches is established to optimize the design parameters of bootstrapped switches, and the calculations based on this model agree well with the measurement results. In order to achieve high linearity, a gradient-mismatch cancelling technique is proposed, which eliminates the first order gradient error of sampling capacitors by combining arrangement of reference control signals and capacitor layout. Fabricated in a 0.18-μm CMOS technology, this ADC occupies 10.16-mm2 area. With statistics-based background calibration of finite opamp gain in the first stage, the ADC achieves 83.5-dB spurious free dynamic range and 63.7-dB signal-to-noise-and distortion ratio respectively, and consumes 393 mW power with a supply voltage of 2 V.

Key words: pipelined ADCbootstrapped switchgradient errorpseudo-random sequence



References:

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[21]

Yin Xiumei, Wei Qi, Xu Lai. A low power 12-b 40-MS/s pipeline ADC[J]. Journal of Semiconductors, 2010, 31(3): 035006. doi: 10.1088/1674-4926/31/3/035006

[22]

Cai Hua, Li Ping, Cen Yuanjun. A 14-bit 80 MS/s CMOS ADC with 84.8 dB SFDR and 72 dB SNDR[J]. Journal of Semiconductors, 2012, 33(2): 025012. doi: 10.1088/1674-4926/33/2/025012

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Choi H C, Yoo P S, Ahn G C. A 14b 150 MS/s 140 mW 2.0 mm2 0.13μm CMOS A/D converter for software-defined radio systems[J]. Int J Circ Theor Appl, 2011, 39: 135. doi: 10.1002/cta.v39.2

[24]

Zhao Lei, Yang Yintang, Zhu Zhangming. SHA-less architecture with enhanced accuracy for pipelined ADC[J]. Journal of Semiconductors, 2012, 33(2): 025010. doi: 10.1088/1674-4926/33/2/025010

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Kester W. Aperture time, aperture jitter, aperture delay time-removing the confusion. Analog Devices, MT-007 Tutorial, Oct, 2008

[26]

Reeder R, Green W, Shilito R. Analog-to-digital converter: clock optimization. Analog Dialogue 42-02, Feb 2008

[1]

Bardsley S, Dillon C, Kummaraguntla R. A 100-dB SFDR 80-MSPS 14-bit 0.35-μm BiCMOS pipeline ADC[J]. IEEE J Solid-State Circuits, 2006, 41(9): 2144. doi: 10.1109/JSSC.2006.880590

[2]

Kazutaka H, Furuta M, Kawahito S. A low-power low-voltage 10-bit 100-MSample/s pipeline A/D converter using capacitance coupling techniques[J]. IEEE J Solid-State Circuits, 2007, 42(4): 757. doi: 10.1109/JSSC.2007.891683

[3]

Cline D W. Noise, speed, and power trade-offs in pipelined analog to digital converters[J]. Diss University of California, Berkeley, 1995.

[4]

Francesco C, Monsurró P, Trifiletti A. A model for the distortion due to switch on-resistance in sample-and-hold circuits[J]. IEEE International Symposium on Circuits and Systems, 2006.

[5]

Andreas G, Tenhunen H. Performance analysis of sampling switches in voltage and frequency domains using Volterra series[J]. Proceedings of the International Symposium on Circuits and Systems, 2004.

[6]

Cai Hua. A 1.8 V low-power 14-bit 20 Msps ADC with 11.2 ENOB[J]. Journal of Semiconductors, 2012, 33(11): 115013. doi: 10.1088/1674-4926/33/11/115013

[7]

Hafiz O A, Wang X, Hurst P J. Immediate calibration of operational amplifier gain error in pipelined ADCs using extended correlated double sampling[J]. IEEE J Solid-State Circuits, 2013, 48(3): 749. doi: 10.1109/JSSC.2012.2230545

[8]

Tseng C J, Chen H W, Shen W T. A 10-b 320-MS/s stage-gain-error self-calibration pipeline ADC[J]. IEEE J Solid-State Circuits, 2012, 47(6): 1334. doi: 10.1109/JSSC.2012.2192655

[9]

Taherzadeh-Sani M, Hamoui A A. Digital background calibration of a 0.4-pJ/step 10-bit pipelined ADC without PN generator in 90-nm digital CMOS[J]. IEEE Asian Solid-State Circuits Conference, 2008.

[10]

Boris M, Boser B E. A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification[J]. IEEE J Solid-State Circuits, 2003, 38(12): 2040. doi: 10.1109/JSSC.2003.819167

[11]

Sun Kexu, He Lenian. A fast combination calibration of foreground and background for pipelined ADCs[J]. Journal of Semiconductors, 2012, 33(6): 065007. doi: 10.1088/1674-4926/33/6/065007

[12]

Daito M, Matsui H, Ueda M. A 14-bit 20-MS/s pipelined ADC with digital distortion calibration[J]. IEEE J Solid-State Circuits, 2006, 41(11): 2417. doi: 10.1109/JSSC.2006.882886

[13]

Ryu S T, Ray S, Song B S. A 14-b linear capacitor self-trimming pipelined ADC[J]. IEEE J Solid-State Circuits, 2004, 39(11): 2046. doi: 10.1109/JSSC.2004.835823

[14]

Singer L, Ho S, Timko M. A 12 b 65 MSample/s CMOS ADC with 82 dB SFDR at 120 MHz[J]. Digest of Technical Papers, IEEE International Solid-State Circuits Conference, 2000.

[15]

Yang W, Kelly D, Mehr I. A 3-V 340-mW 14-b 75-Msample/s CMOS ADC with 85-dB SFDR at Nyquist input[J]. IEEE J Solid-State Circuits, 2001, 36(12): 1931. doi: 10.1109/4.972143

[16]

Park J B, Yoo S M, Kim S W. A 10-b 150-MSample/s 1.8-V 123-mW CMOS A/D converter with 400-MHz input bandwidth[J]. IEEE J Solid-State Circuits, 2004, 39(8): 1335. doi: 10.1109/JSSC.2004.831503

[17]

Abo A M, Gray P R. A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter[J]. IEEE J Solid-State Circuits, 1999, 34(5): 599. doi: 10.1109/4.760369

[18]

Ping C T, Ling T P, Lau G. Analog matching properties process dependency on MIM capacitors[J]. IEEE Regional Symposium on Micro and Nanoelectronics (RSM), 2011.

[19]

ECE1371 Advanced Analog Circuits Lecture 12 Matching and mismatch shaping

[20]

Ye F, Cheng L, Lin K. An 80-MS/s 14-bit pipelined ADC featuring 83 dB SFDR[J]. Analog Integrated Circuits and Signal Processing, 2010, 63(3): 503. doi: 10.1007/s10470-009-9451-2

[21]

Yin Xiumei, Wei Qi, Xu Lai. A low power 12-b 40-MS/s pipeline ADC[J]. Journal of Semiconductors, 2010, 31(3): 035006. doi: 10.1088/1674-4926/31/3/035006

[22]

Cai Hua, Li Ping, Cen Yuanjun. A 14-bit 80 MS/s CMOS ADC with 84.8 dB SFDR and 72 dB SNDR[J]. Journal of Semiconductors, 2012, 33(2): 025012. doi: 10.1088/1674-4926/33/2/025012

[23]

Choi H C, Yoo P S, Ahn G C. A 14b 150 MS/s 140 mW 2.0 mm2 0.13μm CMOS A/D converter for software-defined radio systems[J]. Int J Circ Theor Appl, 2011, 39: 135. doi: 10.1002/cta.v39.2

[24]

Zhao Lei, Yang Yintang, Zhu Zhangming. SHA-less architecture with enhanced accuracy for pipelined ADC[J]. Journal of Semiconductors, 2012, 33(2): 025010. doi: 10.1088/1674-4926/33/2/025010

[25]

Kester W. Aperture time, aperture jitter, aperture delay time-removing the confusion. Analog Devices, MT-007 Tutorial, Oct, 2008

[26]

Reeder R, Green W, Shilito R. Analog-to-digital converter: clock optimization. Analog Dialogue 42-02, Feb 2008

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N Zhao, Q Wei, H Z Yang, H Wang. A 14-bit 100-MS/s CMOS pipelined ADC featuring 83.5-dB SFDR[J]. J. Semicond., 2014, 35(9): 095009. doi: 10.1088/1674-4926/35/9/095009.

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Manuscript received: 29 January 2014 Manuscript revised: 19 February 2014 Online: Published: 01 September 2014

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