J. Semicond. > Volume 36 > Issue 12 > Article Number: 124007

Design of novel DDSCR with embedded PNP structure for ESD protection

Xiuwen Bi , Hailian Liang , Xiaofeng Gu , and Long Huang

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Abstract: A novel dual-directional silicon controlled rectifier(DDSCR) device with embedded PNP structure(DDSCR-PNP) is proposed for electrostatic discharge(ESD) protection, which has greatly reduced latch-up risk owing to the improved holding voltage(Vh). Firstly, the working mechanism of the DDSCR-PNP is analyzed. The theoretical analysis indicates that the proposed device possesses good voltage clamp ability due to the embedded PNP(PNP_2). Then, experimental devices are fabricated in a 0.35μm bipolar-CMOS-DMOS process and measured with a Barth 4002 transmission line pulse testing system. The results show that the Vh of DDSCR-PNP is much higher than that of the conventional DDSCR, and can be further increased by adjusting the P well width. However, the reduced leakage current(IL) of the DDSCR-PNP shows obvious fluctuations when the P well width is increased to more than 12μm. Finally, the factors influencing Vh and IL are investigated by Sentaurus simulations. The results verify that the lateral PNP_2 helps to increase Vh and decrease IL. When the P well width is further increased, the effect of the lateral PNP_2 is weakened, causing an increased IL. The proposed DDSCR-PNP provides an effective and attractive ESD protection solution for high-voltage integrated circuits.

Key words: electrostatic dischargedual-directional silicon controlled rectifiertrigger voltageholding voltageleakage current

Abstract: A novel dual-directional silicon controlled rectifier(DDSCR) device with embedded PNP structure(DDSCR-PNP) is proposed for electrostatic discharge(ESD) protection, which has greatly reduced latch-up risk owing to the improved holding voltage(Vh). Firstly, the working mechanism of the DDSCR-PNP is analyzed. The theoretical analysis indicates that the proposed device possesses good voltage clamp ability due to the embedded PNP(PNP_2). Then, experimental devices are fabricated in a 0.35μm bipolar-CMOS-DMOS process and measured with a Barth 4002 transmission line pulse testing system. The results show that the Vh of DDSCR-PNP is much higher than that of the conventional DDSCR, and can be further increased by adjusting the P well width. However, the reduced leakage current(IL) of the DDSCR-PNP shows obvious fluctuations when the P well width is increased to more than 12μm. Finally, the factors influencing Vh and IL are investigated by Sentaurus simulations. The results verify that the lateral PNP_2 helps to increase Vh and decrease IL. When the P well width is further increased, the effect of the lateral PNP_2 is weakened, causing an increased IL. The proposed DDSCR-PNP provides an effective and attractive ESD protection solution for high-voltage integrated circuits.

Key words: electrostatic dischargedual-directional silicon controlled rectifiertrigger voltageholding voltageleakage current



References:

[1]

Ker M D, Hsu K C. Overview of on-chip electrostatic discharge protection design with SCR-based devices in CMOS integrated circuits[J]. IEEE Trans Device Mater Reliab, 2005, 5(2): 235.

[2]

Liu J Z, Liu Z W, Jia Z. A novel DTSCR with a variation lateral base doping structure to improve turn-on speed for ESD protection[J]. Journal of Semiconductors, 2014, 35(6): 064010.

[3]

Parthasarathy V, Khemka V, Zhu R. A double RESURF LDMOS with drain profile engineering for improved ESD robustness[J]. Electron Device Lett, 2002, 23(4): 212.

[4]

Wang Y, Lu G Y, Cao J. Analysis of dummy-gate dual-directional SCR(dSCR) device for ESD protection[J]. The 20th IEEE international Symposium on the Physical and Failure Analysis of Integrated Circuits(IPFA), 2013: 720.

[5]

Liang H L, Dong S R, Gu X F. ESD protection design of DDSCR structure based on the 0.5 μm BCD process[J]. Journal of Zhejiang University(Engineering Science), 2013, 47(11): 2046.

[6]

Wang Z H, Feng H G, Zhang R Y. A review on RF ESD protection design[J]. IEEE Trans Electron Devices, 2005, 5(7): 1304.

[7]

Chen G, Feng H G, Albert W. A systematic study of ESD protection structures for RF ICs[J]. Radio Frequency Integrated Circuits Symposium(RFIC), 2003: 347.

[8]

Liu J, Lin L, Wang X. Design optimization of adjustable triggering dual-polarity ESD protection structures[J]. Bipolar/BiCMOS Circuits and Technology Meeting(BCTM), 2010: 149.

[9]

Liu J, Lin L, Wang X. Vast-fast low-triggering LTdSCR ESD protection structure for RF ICs in CMOS[J]. Radio Frequency Integrated Circuits Symposium(RFIC), 2010: 233.

[10]

Liu J, Chen H Y. A dual-polarity ESD protection device based on SCR[J]. Microelectronics, 2008, 38(4): 485.

[11]

Vashchenko V A, LaFonteese K G, Korablev K G. Lateral PNP BJT ESD protection devices[J]. Bipolar/BiCMOS Circuits and Technology Meeting(BCTM), 2008: 53.

[1]

Ker M D, Hsu K C. Overview of on-chip electrostatic discharge protection design with SCR-based devices in CMOS integrated circuits[J]. IEEE Trans Device Mater Reliab, 2005, 5(2): 235.

[2]

Liu J Z, Liu Z W, Jia Z. A novel DTSCR with a variation lateral base doping structure to improve turn-on speed for ESD protection[J]. Journal of Semiconductors, 2014, 35(6): 064010.

[3]

Parthasarathy V, Khemka V, Zhu R. A double RESURF LDMOS with drain profile engineering for improved ESD robustness[J]. Electron Device Lett, 2002, 23(4): 212.

[4]

Wang Y, Lu G Y, Cao J. Analysis of dummy-gate dual-directional SCR(dSCR) device for ESD protection[J]. The 20th IEEE international Symposium on the Physical and Failure Analysis of Integrated Circuits(IPFA), 2013: 720.

[5]

Liang H L, Dong S R, Gu X F. ESD protection design of DDSCR structure based on the 0.5 μm BCD process[J]. Journal of Zhejiang University(Engineering Science), 2013, 47(11): 2046.

[6]

Wang Z H, Feng H G, Zhang R Y. A review on RF ESD protection design[J]. IEEE Trans Electron Devices, 2005, 5(7): 1304.

[7]

Chen G, Feng H G, Albert W. A systematic study of ESD protection structures for RF ICs[J]. Radio Frequency Integrated Circuits Symposium(RFIC), 2003: 347.

[8]

Liu J, Lin L, Wang X. Design optimization of adjustable triggering dual-polarity ESD protection structures[J]. Bipolar/BiCMOS Circuits and Technology Meeting(BCTM), 2010: 149.

[9]

Liu J, Lin L, Wang X. Vast-fast low-triggering LTdSCR ESD protection structure for RF ICs in CMOS[J]. Radio Frequency Integrated Circuits Symposium(RFIC), 2010: 233.

[10]

Liu J, Chen H Y. A dual-polarity ESD protection device based on SCR[J]. Microelectronics, 2008, 38(4): 485.

[11]

Vashchenko V A, LaFonteese K G, Korablev K G. Lateral PNP BJT ESD protection devices[J]. Bipolar/BiCMOS Circuits and Technology Meeting(BCTM), 2008: 53.

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X W Bi, H L Liang, X F Gu, L Huang. Design of novel DDSCR with embedded PNP structure for ESD protection[J]. J. Semicond., 2015, 36(12): 124007. doi: 10.1088/1674-4926/36/12/124007.

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History

Manuscript received: 07 May 2015 Manuscript revised: Online: Published: 01 December 2015

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