J. Semicond. > Volume 36 > Issue 12 > Article Number: 124007

Design of novel DDSCR with embedded PNP structure for ESD protection

Xiuwen Bi , Hailian Liang , Xiaofeng Gu , and Long Huang

+ Author Affiliations + Find other works by these authors

PDF

Abstract: A novel dual-directional silicon controlled rectifier(DDSCR) device with embedded PNP structure(DDSCR-PNP) is proposed for electrostatic discharge(ESD) protection, which has greatly reduced latch-up risk owing to the improved holding voltage(Vh). Firstly, the working mechanism of the DDSCR-PNP is analyzed. The theoretical analysis indicates that the proposed device possesses good voltage clamp ability due to the embedded PNP(PNP_2). Then, experimental devices are fabricated in a 0.35μm bipolar-CMOS-DMOS process and measured with a Barth 4002 transmission line pulse testing system. The results show that the Vh of DDSCR-PNP is much higher than that of the conventional DDSCR, and can be further increased by adjusting the P well width. However, the reduced leakage current(IL) of the DDSCR-PNP shows obvious fluctuations when the P well width is increased to more than 12μm. Finally, the factors influencing Vh and IL are investigated by Sentaurus simulations. The results verify that the lateral PNP_2 helps to increase Vh and decrease IL. When the P well width is further increased, the effect of the lateral PNP_2 is weakened, causing an increased IL. The proposed DDSCR-PNP provides an effective and attractive ESD protection solution for high-voltage integrated circuits.

Key words: electrostatic dischargedual-directional silicon controlled rectifiertrigger voltageholding voltageleakage current

Abstract: A novel dual-directional silicon controlled rectifier(DDSCR) device with embedded PNP structure(DDSCR-PNP) is proposed for electrostatic discharge(ESD) protection, which has greatly reduced latch-up risk owing to the improved holding voltage(Vh). Firstly, the working mechanism of the DDSCR-PNP is analyzed. The theoretical analysis indicates that the proposed device possesses good voltage clamp ability due to the embedded PNP(PNP_2). Then, experimental devices are fabricated in a 0.35μm bipolar-CMOS-DMOS process and measured with a Barth 4002 transmission line pulse testing system. The results show that the Vh of DDSCR-PNP is much higher than that of the conventional DDSCR, and can be further increased by adjusting the P well width. However, the reduced leakage current(IL) of the DDSCR-PNP shows obvious fluctuations when the P well width is increased to more than 12μm. Finally, the factors influencing Vh and IL are investigated by Sentaurus simulations. The results verify that the lateral PNP_2 helps to increase Vh and decrease IL. When the P well width is further increased, the effect of the lateral PNP_2 is weakened, causing an increased IL. The proposed DDSCR-PNP provides an effective and attractive ESD protection solution for high-voltage integrated circuits.

Key words: electrostatic dischargedual-directional silicon controlled rectifiertrigger voltageholding voltageleakage current



References:

[1]

Ker M D, Hsu K C. Overview of on-chip electrostatic discharge protection design with SCR-based devices in CMOS integrated circuits[J]. IEEE Trans Device Mater Reliab, 2005, 5(2): 235.

[2]

Liu J Z, Liu Z W, Jia Z. A novel DTSCR with a variation lateral base doping structure to improve turn-on speed for ESD protection[J]. Journal of Semiconductors, 2014, 35(6): 064010.

[3]

Parthasarathy V, Khemka V, Zhu R. A double RESURF LDMOS with drain profile engineering for improved ESD robustness[J]. Electron Device Lett, 2002, 23(4): 212.

[4]

Wang Y, Lu G Y, Cao J. Analysis of dummy-gate dual-directional SCR(dSCR) device for ESD protection[J]. The 20th IEEE international Symposium on the Physical and Failure Analysis of Integrated Circuits(IPFA), 2013: 720.

[5]

Liang H L, Dong S R, Gu X F. ESD protection design of DDSCR structure based on the 0.5 μm BCD process[J]. Journal of Zhejiang University(Engineering Science), 2013, 47(11): 2046.

[6]

Wang Z H, Feng H G, Zhang R Y. A review on RF ESD protection design[J]. IEEE Trans Electron Devices, 2005, 5(7): 1304.

[7]

Chen G, Feng H G, Albert W. A systematic study of ESD protection structures for RF ICs[J]. Radio Frequency Integrated Circuits Symposium(RFIC), 2003: 347.

[8]

Liu J, Lin L, Wang X. Design optimization of adjustable triggering dual-polarity ESD protection structures[J]. Bipolar/BiCMOS Circuits and Technology Meeting(BCTM), 2010: 149.

[9]

Liu J, Lin L, Wang X. Vast-fast low-triggering LTdSCR ESD protection structure for RF ICs in CMOS[J]. Radio Frequency Integrated Circuits Symposium(RFIC), 2010: 233.

[10]

Liu J, Chen H Y. A dual-polarity ESD protection device based on SCR[J]. Microelectronics, 2008, 38(4): 485.

[11]

Vashchenko V A, LaFonteese K G, Korablev K G. Lateral PNP BJT ESD protection devices[J]. Bipolar/BiCMOS Circuits and Technology Meeting(BCTM), 2008: 53.

[1]

Ker M D, Hsu K C. Overview of on-chip electrostatic discharge protection design with SCR-based devices in CMOS integrated circuits[J]. IEEE Trans Device Mater Reliab, 2005, 5(2): 235.

[2]

Liu J Z, Liu Z W, Jia Z. A novel DTSCR with a variation lateral base doping structure to improve turn-on speed for ESD protection[J]. Journal of Semiconductors, 2014, 35(6): 064010.

[3]

Parthasarathy V, Khemka V, Zhu R. A double RESURF LDMOS with drain profile engineering for improved ESD robustness[J]. Electron Device Lett, 2002, 23(4): 212.

[4]

Wang Y, Lu G Y, Cao J. Analysis of dummy-gate dual-directional SCR(dSCR) device for ESD protection[J]. The 20th IEEE international Symposium on the Physical and Failure Analysis of Integrated Circuits(IPFA), 2013: 720.

[5]

Liang H L, Dong S R, Gu X F. ESD protection design of DDSCR structure based on the 0.5 μm BCD process[J]. Journal of Zhejiang University(Engineering Science), 2013, 47(11): 2046.

[6]

Wang Z H, Feng H G, Zhang R Y. A review on RF ESD protection design[J]. IEEE Trans Electron Devices, 2005, 5(7): 1304.

[7]

Chen G, Feng H G, Albert W. A systematic study of ESD protection structures for RF ICs[J]. Radio Frequency Integrated Circuits Symposium(RFIC), 2003: 347.

[8]

Liu J, Lin L, Wang X. Design optimization of adjustable triggering dual-polarity ESD protection structures[J]. Bipolar/BiCMOS Circuits and Technology Meeting(BCTM), 2010: 149.

[9]

Liu J, Lin L, Wang X. Vast-fast low-triggering LTdSCR ESD protection structure for RF ICs in CMOS[J]. Radio Frequency Integrated Circuits Symposium(RFIC), 2010: 233.

[10]

Liu J, Chen H Y. A dual-polarity ESD protection device based on SCR[J]. Microelectronics, 2008, 38(4): 485.

[11]

Vashchenko V A, LaFonteese K G, Korablev K G. Lateral PNP BJT ESD protection devices[J]. Bipolar/BiCMOS Circuits and Technology Meeting(BCTM), 2008: 53.

[1]

Hailian Liang, Shurong Dong, Xiaofeng Gu, Lei Zhong, Jian Wu, Zongguang Yu. Investigation of the trigger voltage walk-in effect in LDMOS for high-voltage ESD protection. J. Semicond., 2014, 35(9): 094005. doi: 10.1088/1674-4926/35/9/094005

[2]

Li Tian, Jianbing Cheng, Cairong Zhang, Li Shen, Lei Wang. Design and analysis of a NMOS triggered LIGBT structure for electrostatic discharge protection. J. Semicond., 2019, 40(5): 052402. doi: 10.1088/1674-4926/40/5/052402

[3]

Gong Na, Wang Jinhui, Guo Baozeng, Pang Jiao. Temperature and Process Variations Aware Dual Threshold Voltage Footed Domino Circuits Leakage Management. J. Semicond., 2008, 29(12): 2364.

[4]

Hongwei Pan, Siyang Liu, Weifeng Sun. A novel latch-up free SCR-LDMOS with high holding voltage for a power-rail ESD clamp. J. Semicond., 2013, 34(1): 014007. doi: 10.1088/1674-4926/34/1/014007

[5]

Zhaonian Yang, Hongxia Liu, Shulong Wang. A low leakage power-rail ESD detection circuit with a modified RC network for a 90-nm CMOS process. J. Semicond., 2013, 34(4): 045010. doi: 10.1088/1674-4926/34/4/045010

[6]

Zhu Jing, Qian Qinsong, Sun Weifeng, Liu Siyang. Analysis of trigger behavior of high voltage LDMOS under TLP and VFTLP stress. J. Semicond., 2010, 31(1): 014003. doi: 10.1088/1674-4926/31/1/014003

[7]

Zhu Kehan, Yu Zongguang, Dong Shurong, Han Yan. Design Analysis of a Novel Low Triggering Voltage Dual Direction SCR ESD Device in 0.18μm Mixed Mode RFCMOS Technology. J. Semicond., 2008, 29(11): 2164.

[8]

O.Ya Olikh, K.V. Voitenko, R.M. Burbelo, JaM. Olikh. Effect of ultrasound on reverse leakage current of silicon Schottky barrier structure. J. Semicond., 2016, 37(12): 122002. doi: 10.1088/1674-4926/37/12/122002

[9]

Lin Lijuan, Jiang Lingli, Fan Hang, Zhang Bo. Impact of parasitic resistance on the ESD robustness of high-voltage devices. J. Semicond., 2012, 33(1): 014005. doi: 10.1088/1674-4926/33/1/014005

[10]

Wang Yuan, Chen Zhongjian, Jia Song, Lu Wengao, Fu Yiling, Ji Lijiu. Novel Electrostatic Discharge Protection Design Method. J. Semicond., 2007, 28(7): 1156.

[11]

Song Li, Chuanbin Zeng, Jiajun Luo, Zhengsheng Han. The abnormal electrostatic discharge of a no-connect metal cover in a ceramic packaging device. J. Semicond., 2013, 34(8): 084007. doi: 10.1088/1674-4926/34/8/084007

[12]

Xue Jiying, Li Tao, Yu Zhiping. Accurate and fast table look-up models for leakage current analysis in 65 nm CMOS technology. J. Semicond., 2009, 30(2): 024004. doi: 10.1088/1674-4926/30/2/024004

[13]

Wanjun Chen, Jing Zhang, Bo Zhang, Kevin Jing Chen . Fluorine-plasma surface treatment for gate forward leakage current reduction in AlGaN/GaN HEMTs. J. Semicond., 2013, 34(2): 024003. doi: 10.1088/1674-4926/34/2/024003

[14]

Huaguo Liang, Hui Xu, Zhengfeng Huang, Maoxiang Yi. A low-leakage and NBTI-mitigated N-type domino logic. J. Semicond., 2014, 35(1): 015009. doi: 10.1088/1674-4926/35/1/015009

[15]

Guo Baozeng, Gong Na, Wang Jinhui. Designing Leakage-Tolerant and Noise-Immune Enhanced Low Power Wide OR Dominos in Sub-70nm CMOS Technologies. J. Semicond., 2006, 27(5): 804.

[16]

Jianwei Wu, Zongguang Yu, Genshen Hong, Rubin Xie. Design of GGNMOS ESD protection device for radiation-hardened 0.18 μm CMOS process. J. Semicond., 2020, 41(12): 122403. doi: 10.1088/1674-4926/41/12/122403

[17]

Junjun Yuan, Zebo Fang, Yanyan Zhu, Bo Yao, Shiyan Liu, Gang He, Yongsheng Tan. Current mechanism and band alignment of Al(Pt)/HfGdO/Ge capacitors. J. Semicond., 2016, 37(3): 034006. doi: 10.1088/1674-4926/37/3/034006

[18]

Jiang Yibo, Zeng Chuanbin, Du Huan, Luo Jiajun, Han Zhengsheng. Holding-voltage drift of a silicon-controlled rectifier with different film thicknesses in silicon-on-insulator technology. J. Semicond., 2012, 33(3): 034006. doi: 10.1088/1674-4926/33/3/034006

[19]

Yang Zhaonian, Liu Hongxia, Li Li, Zhuo Qingqing. A novel high performance ESD power clamp circuit with a small area. J. Semicond., 2012, 33(9): 095006. doi: 10.1088/1674-4926/33/9/095006

[20]

Wang Albert, Lin Lin, Wang Xin, Liu Hainan, Zhou Yumei. Emerging Challenges in ESD Protection for RF ICs in CMOS. J. Semicond., 2008, 29(4): 628.

Search

Advanced Search >>

GET CITATION

X W Bi, H L Liang, X F Gu, L Huang. Design of novel DDSCR with embedded PNP structure for ESD protection[J]. J. Semicond., 2015, 36(12): 124007. doi: 10.1088/1674-4926/36/12/124007.

Export: BibTex EndNote

Article Metrics

Article views: 1342 Times PDF downloads: 9 Times Cited by: 0 Times

History

Manuscript received: 07 May 2015 Manuscript revised: Online: Published: 01 December 2015

Email This Article

User name:
Email:*请输入正确邮箱
Code:*验证码错误