J. Semicond. > Volume 36 > Issue 12 > Article Number: 125004

A trimming technique for capacitive SAR ADC as sensor interface

Ke Liu , , Zhankun Du , Li Shao and Xiao Ma

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Abstract: This work presented a trimming technique and algorithm applied in a capacitive successive approximation register(SAR) analog to digital converter(ADC) for a sensor interface, which can be integrated with the preceding sensor and the following controlling circuit. Without spending a special calibration phase or adding complicated functions, this circuit keeps a 12-bit resolution by trimming the capacitor array. Its merits of low power and small area make it suitable to be embedded in a power and cost sensitive system such as a battery-supplied sensor network node. The prototype 12-bit ADC is implemented by 0.5μm 2P3M CMOS technology, with the wide supply range of 2-5 V, its power consumption is only 300μA at a sampling speed of 200 kHz.

Key words: SARADCtrimmingsensorCMOS

Abstract: This work presented a trimming technique and algorithm applied in a capacitive successive approximation register(SAR) analog to digital converter(ADC) for a sensor interface, which can be integrated with the preceding sensor and the following controlling circuit. Without spending a special calibration phase or adding complicated functions, this circuit keeps a 12-bit resolution by trimming the capacitor array. Its merits of low power and small area make it suitable to be embedded in a power and cost sensitive system such as a battery-supplied sensor network node. The prototype 12-bit ADC is implemented by 0.5μm 2P3M CMOS technology, with the wide supply range of 2-5 V, its power consumption is only 300μA at a sampling speed of 200 kHz.

Key words: SARADCtrimmingsensorCMOS



References:

[1]

McNeill J A, Ka Y C, Coln M C W. All-digital background calibration of a successive approximation ADC using the "split ADC" architecture[J]. IEEE Trans Circuits Syst I:Regular Papers, 2011, 58: 2355.

[2]

Liu C C, Chang S J, Huang G Y. A 10 b 100 MS/s 1.13 mW SAR ADC with binary scaled error compensation[J]. IEEE International Solid State Circuits Conference, 2010, 386.

[3]

Gan J, Shouli Y, Abraham J. Effects of noise and nonlinearity on the calibration of a non-binary capacitor array in a successive approximation analog-to-digital converter[J]. Proceedings of Asia and South Pacific Design Automation Conference, 2004: 292.

[4]

Promitzer G. 12-bit low-power fully differential switched capacitor noncalibrating successive approximation ADC with 1 MS/s[J]. IEEE J Solid-State Circuits, 2001, 36(7): 1138.

[5]

Shrivastava A. 12-bit non-calibrating noise-immune redundant SAR ADC for system-on-a-chip[J]. IEEE International Symposium on Circuits and Systems, 2006: 1515.

[6]

De Wit M, Tan K S, Hester R K. A low-power 12-b analog-to-digital converter with on-chip precision trimming[J]. IEEE J Solid-State Circuits, 1993, 28(4): 455.

[7]

Zhou W, Lee C. Analysis of capacitor mismatch effect in SAR A/D converter[J]. Microelectronics, 2007, 37(2): 199.

[8]

Zhong L, Yang H, Zhang C. Design of an embedded CMOS CR SAR ADC for low power applications in bio-sensor SOC[J]. 7th International Conference on ASIC, 2007: 668.

[9]

Hong Hui, Li Shiliang, Zhou Tao. Design of a low power 10 bit 300 ksps multi-channel SAR ADC for wireless sensor network applications[J]. Journal of Semiconductors, 2015, 36(4): 045009.

[10]

Agnes A, Bonizzoni E, Maicovati P. A 9.4-ENOB 1 V 3.8 μW 100 kS/s SAR ADC with time-domain comparator[J]. IEEE International Solid-State Circuits Conference, 2008, 51(246).

[1]

McNeill J A, Ka Y C, Coln M C W. All-digital background calibration of a successive approximation ADC using the "split ADC" architecture[J]. IEEE Trans Circuits Syst I:Regular Papers, 2011, 58: 2355.

[2]

Liu C C, Chang S J, Huang G Y. A 10 b 100 MS/s 1.13 mW SAR ADC with binary scaled error compensation[J]. IEEE International Solid State Circuits Conference, 2010, 386.

[3]

Gan J, Shouli Y, Abraham J. Effects of noise and nonlinearity on the calibration of a non-binary capacitor array in a successive approximation analog-to-digital converter[J]. Proceedings of Asia and South Pacific Design Automation Conference, 2004: 292.

[4]

Promitzer G. 12-bit low-power fully differential switched capacitor noncalibrating successive approximation ADC with 1 MS/s[J]. IEEE J Solid-State Circuits, 2001, 36(7): 1138.

[5]

Shrivastava A. 12-bit non-calibrating noise-immune redundant SAR ADC for system-on-a-chip[J]. IEEE International Symposium on Circuits and Systems, 2006: 1515.

[6]

De Wit M, Tan K S, Hester R K. A low-power 12-b analog-to-digital converter with on-chip precision trimming[J]. IEEE J Solid-State Circuits, 1993, 28(4): 455.

[7]

Zhou W, Lee C. Analysis of capacitor mismatch effect in SAR A/D converter[J]. Microelectronics, 2007, 37(2): 199.

[8]

Zhong L, Yang H, Zhang C. Design of an embedded CMOS CR SAR ADC for low power applications in bio-sensor SOC[J]. 7th International Conference on ASIC, 2007: 668.

[9]

Hong Hui, Li Shiliang, Zhou Tao. Design of a low power 10 bit 300 ksps multi-channel SAR ADC for wireless sensor network applications[J]. Journal of Semiconductors, 2015, 36(4): 045009.

[10]

Agnes A, Bonizzoni E, Maicovati P. A 9.4-ENOB 1 V 3.8 μW 100 kS/s SAR ADC with time-domain comparator[J]. IEEE International Solid-State Circuits Conference, 2008, 51(246).

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K Liu, Z K Du, L Shao, X Ma. A trimming technique for capacitive SAR ADC as sensor interface[J]. J. Semicond., 2015, 36(12): 125004. doi: 10.1088/1674-4926/36/12/125004.

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Manuscript received: 01 April 2015 Manuscript revised: Online: Published: 01 December 2015

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