J. Semicond. > Volume 36 > Issue 12 > Article Number: 126001

A new kind of chelating agent with low pH value applied in the TSV CMP slurry

Jiao Hong 1, 2, , , Yuling Liu 1, 2, , Baoguo Zhang 1, 2, , Xinhuan Niu 1, 2, and Liying Han 1,

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Abstract: TSV(through silicon via) is an emerging technology, which can realize micromation compared with the conventional packaging and extend Moore's law. Chemical mechanical polishing(CMP) is one of the most important steps in the process of TSV manufacture, and it is an enabling technology to extend Moore's law in the past two decades. Low pressure, low abrasive and low pH value are the main requirements for copper interconnection. In this paper, the effect of different kinds of TSV slurry with FA/O Ⅱ or FA/O IV type chelating agent on CMP are studied. All kinds of slurry used in this study are alkaline with no added inhibitors. From the experiment results, it can be seen that the copper removal rate and surface roughness achieved by using the FA/O IV type chelating agent with a low pH value is superior to using the FA/O Ⅱ type chelating agent.

Key words: low pH valuealkaline slurryremoval rateroughnessoptoelectronic integrated circuits

Abstract: TSV(through silicon via) is an emerging technology, which can realize micromation compared with the conventional packaging and extend Moore's law. Chemical mechanical polishing(CMP) is one of the most important steps in the process of TSV manufacture, and it is an enabling technology to extend Moore's law in the past two decades. Low pressure, low abrasive and low pH value are the main requirements for copper interconnection. In this paper, the effect of different kinds of TSV slurry with FA/O Ⅱ or FA/O IV type chelating agent on CMP are studied. All kinds of slurry used in this study are alkaline with no added inhibitors. From the experiment results, it can be seen that the copper removal rate and surface roughness achieved by using the FA/O IV type chelating agent with a low pH value is superior to using the FA/O Ⅱ type chelating agent.

Key words: low pH valuealkaline slurryremoval rateroughnessoptoelectronic integrated circuits



References:

[1]

Chua T T, Ho S W, Li H Y. 3D interconnection process development and integration with low stress TSV[J]. IEEE Proceedings 60th Electronic Components and Technology Conference(ECTC), 2010: 798.

[2]

Wu Heng, Tang Zhen'an, Wang Zhu. Simulation of through via bottom-up copper plating with accelerator for the filling of TSVs[J]. Journal of Semiconductors, 2013, 34(9): 096001.

[3]

Chua T T, Ho S W, Li H Y. 3D interconnection process development and integration with low stress TSV[J]. 2010 Electronic Components and Technology Conference, 2010, 10(972): 798.

[4]

Ma Suohui, Wang Shengli, Liu Yuling. Alkaline barrier slurry applied in TSV chemical mechanical planarization[J]. Journal of Semiconductors, 2014, 35(2): 026002.

[5]

Liu Xiaoxian, Zhu Zhangming, Yang Yintang. Impedance matching for the reduction of signal reflection in high speed multilevel three-dimensional integrated chips[J]. Journal of Semiconductors, 2014, 35(1): 015008.

[6]

Wu X D. Research status of through silicon via interconnection for 3D integration technology[J]. Electronics and Packaging, 2012, 12(9): 1.

[7]

Wei Zhen, Li Xiaochun, Mao Junfa. An accurate RLGC circuit model for dual tapered TSV structure[J]. Journal of Semiconductors, 2014, 35(9): 095008.

[8]

Liu Song, Shan Guangbao, Xie Chengmin. A transmission line-type electrical model for tapered TSV considering MOS effect and frequency-dependent behavior[J]. Journal of Semiconductors, 2015, 36(2): 024009.

[9]

Tsai T C, Tsao W C, Lin W. CMP process development for the via-middle 3D TSV applications at 28 nm[J]. Microelectron Eng, 2012, 92: 29.

[10]

Chen J C, Lau J H, Tzeng P J. Effects of slurry in Cu chemical mechanical polishing(CMP) of TSVs for 3-D IC integration[J]. IEEE Trans Components Packaging & Manufacturing Technology, 2012, 2(6): 956.

[11]

Gao S, Kwong D L. 3D IC integration with TSV current progress and future outlook[J]. Institute of Microelectronics, 2010, 9: 1.

[12]

Zhao Yingbo, Dong Gang, Yang Yintang. Analysis and optimization of TSV-TSV coupling in three-dimensional integrated circuits[J]. Journal of Semiconductors, 2015, 36(4): 045011.

[13]

Hsu A. TSV CMP technology, market, & challenges[J]. .

[14]

Rao V S, Wee H S, Vincent L W S. TSV interposer fabrication for 3D IC packaging[J]. 11th Electronics Packaging Technology Conference, 2009: 431.

[15]

Vincent L W S, Khan N, Ebin L. Cu via exposure by backgrinding for TSV applications[J]. 9th Electronics Packaging Technology Conference, 2007: 233.

[16]

Murata J, Sadakuni S, Okamoto T. Structural and chemical characteristics of atomically smooth GaN surfaces prepared by abrasive-free polishing with Pt catalyst[J]. J Crystal Growth, 2012, 349: 83.

[17]

Zheng J P, Roy D. Electrochemical examination of surface films formed during chemical mechanical planarization of copper in acetic acid and dodecyl sulfate solutions[J]. Thin Solid Films, 2009, 517(16): 4587.

[18]

Ng D, Kulkarni M, Johnson J. Oxidation and removal mechanisms during chemical-mechanical planarization[J]. Wear, 2007, 263: 1477.

[19]

Amanokura J, Ono H, Hombo K. Development of high speed copper CMP slurry for TSV application based on friction analysis[J]. IEEE CPMT Symposium Japan, 2010.

[20]

Takahashi K, Taguchi Y, Tomisaka M. Process integration of 3D chip stack with vertical interconnection[J]. Electronic Components and Technology Conference, 2004: 601.

[21]

Chen J C, Tzeng P J, Chen S C. Impact of slurry in Cu CMP(chemical mechanical polishing) on Cu topography of through silicon vias(TSVs), re-distribution layers, and Cu exposure[J]. Electronic Components and Technology Conference, 2011.

[1]

Chua T T, Ho S W, Li H Y. 3D interconnection process development and integration with low stress TSV[J]. IEEE Proceedings 60th Electronic Components and Technology Conference(ECTC), 2010: 798.

[2]

Wu Heng, Tang Zhen'an, Wang Zhu. Simulation of through via bottom-up copper plating with accelerator for the filling of TSVs[J]. Journal of Semiconductors, 2013, 34(9): 096001.

[3]

Chua T T, Ho S W, Li H Y. 3D interconnection process development and integration with low stress TSV[J]. 2010 Electronic Components and Technology Conference, 2010, 10(972): 798.

[4]

Ma Suohui, Wang Shengli, Liu Yuling. Alkaline barrier slurry applied in TSV chemical mechanical planarization[J]. Journal of Semiconductors, 2014, 35(2): 026002.

[5]

Liu Xiaoxian, Zhu Zhangming, Yang Yintang. Impedance matching for the reduction of signal reflection in high speed multilevel three-dimensional integrated chips[J]. Journal of Semiconductors, 2014, 35(1): 015008.

[6]

Wu X D. Research status of through silicon via interconnection for 3D integration technology[J]. Electronics and Packaging, 2012, 12(9): 1.

[7]

Wei Zhen, Li Xiaochun, Mao Junfa. An accurate RLGC circuit model for dual tapered TSV structure[J]. Journal of Semiconductors, 2014, 35(9): 095008.

[8]

Liu Song, Shan Guangbao, Xie Chengmin. A transmission line-type electrical model for tapered TSV considering MOS effect and frequency-dependent behavior[J]. Journal of Semiconductors, 2015, 36(2): 024009.

[9]

Tsai T C, Tsao W C, Lin W. CMP process development for the via-middle 3D TSV applications at 28 nm[J]. Microelectron Eng, 2012, 92: 29.

[10]

Chen J C, Lau J H, Tzeng P J. Effects of slurry in Cu chemical mechanical polishing(CMP) of TSVs for 3-D IC integration[J]. IEEE Trans Components Packaging & Manufacturing Technology, 2012, 2(6): 956.

[11]

Gao S, Kwong D L. 3D IC integration with TSV current progress and future outlook[J]. Institute of Microelectronics, 2010, 9: 1.

[12]

Zhao Yingbo, Dong Gang, Yang Yintang. Analysis and optimization of TSV-TSV coupling in three-dimensional integrated circuits[J]. Journal of Semiconductors, 2015, 36(4): 045011.

[13]

Hsu A. TSV CMP technology, market, & challenges[J]. .

[14]

Rao V S, Wee H S, Vincent L W S. TSV interposer fabrication for 3D IC packaging[J]. 11th Electronics Packaging Technology Conference, 2009: 431.

[15]

Vincent L W S, Khan N, Ebin L. Cu via exposure by backgrinding for TSV applications[J]. 9th Electronics Packaging Technology Conference, 2007: 233.

[16]

Murata J, Sadakuni S, Okamoto T. Structural and chemical characteristics of atomically smooth GaN surfaces prepared by abrasive-free polishing with Pt catalyst[J]. J Crystal Growth, 2012, 349: 83.

[17]

Zheng J P, Roy D. Electrochemical examination of surface films formed during chemical mechanical planarization of copper in acetic acid and dodecyl sulfate solutions[J]. Thin Solid Films, 2009, 517(16): 4587.

[18]

Ng D, Kulkarni M, Johnson J. Oxidation and removal mechanisms during chemical-mechanical planarization[J]. Wear, 2007, 263: 1477.

[19]

Amanokura J, Ono H, Hombo K. Development of high speed copper CMP slurry for TSV application based on friction analysis[J]. IEEE CPMT Symposium Japan, 2010.

[20]

Takahashi K, Taguchi Y, Tomisaka M. Process integration of 3D chip stack with vertical interconnection[J]. Electronic Components and Technology Conference, 2004: 601.

[21]

Chen J C, Tzeng P J, Chen S C. Impact of slurry in Cu CMP(chemical mechanical polishing) on Cu topography of through silicon vias(TSVs), re-distribution layers, and Cu exposure[J]. Electronic Components and Technology Conference, 2011.

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J Hong, Y L Liu, B G Zhang, X H Niu, L Y Han. A new kind of chelating agent with low pH value applied in the TSV CMP slurry[J]. J. Semicond., 2015, 36(12): 126001. doi: 10.1088/1674-4926/36/12/126001.

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Manuscript received: 17 March 2015 Manuscript revised: Online: Published: 01 December 2015

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