J. Semicond. > 2015, Volume 36 > Issue 2 > 024003
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SEMICONDUCTOR DEVICES

High performance 20 nm GaSb/InAs junctionless tunnel field effect transistor for low power supply

Pranav Kumar Asthana

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 Corresponding author: Pranav Kumar Asthana, E-mail: pranavasthana32@gmail.com

DOI: 10.1088/1674-4926/36/2/024003

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Abstract: We present a GaSb/InAs junctionless tunnel FET and investigate its static device characteristics. The proposed structure presents tremendous performance at a very low supply voltage of 0.4 V. The key idea is to the present device architecture, which can be exploited as a digital switching device for sub 20 nm technology. Numerical simulations resulted in an IOFF of ～8 × 10-17 A/μm, ION of ～ 9 μA/μm, ION/IOFF of ～1 × 1011, subthreshold slope of 9.33 mV/dec and DIBL of ～ 87 mV/V for GaSb/InAs JLTFET at a temperature of 300 K, gate length of 20 nm, HfO2 gate dielectric thickness of 2 nm, film thickness of 10 nm, low-k spacer thickness of 10 nm and VDD of 0.4 V.

Key words: band tunneling (BTBT), tunnel field effect transistor (TFET), junctionless tunnel field effect transistor (JLTFET), ION/IOFF ratio, low power, digital switching



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Fig. 1.  Cross sectional view of device structure, 20 nm GaSb/InAs junctionless tunnel field effect transistor (JLTFET).

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Fig. 2.  Electron and hole concentration profile of GaSb/InAs JLTFET at channel and SiO$_{2}$ interface (top) as a function of position along the $x$-direction in the ON-state ($V_{\rm DS}$ $=$ 0.4 V, $V_{\rm GS}$ $=$ 0.4 V) and OFF-state ($V_{\rm DS}$ $=$ 0.4 V, $V_{\rm GS}$ $=$ 0 V).

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Fig. 3.  Energy band diagram in the ON-state ($V_{\rm DS}$ $=$ 0.4 V, $V_{\rm GS}$ $=$ 0.4 V) and OFF-state ($V_{\rm DS}$ $=$ 0.4 V, $V_{\rm GS}$ $=$ 0 V) for GaSb/InAs JLTFET along the $x$-direction at the channel and gate dielectric interface.

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Fig. 4.  Lateral electric field of GaSb/InAs JLTFET as a function of position along the $x$-direction in OFF-state ($V_{\rm DS}$ $=$ 0.4 V, $V_{\rm GS}$ $=$ 0~V) and ON-state ($V_{\rm DS}$ $=$ 0.4 V, $V_{\rm GS}$ $=$ 0.4 V) at the channel and gate dielectric interface (top).

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Fig. 5.  Drain to source potential pattern of GaSb/InAs JLTFET as a function of position along the $x$-direction in the OFF-state ($V_{\rm DS}$ $=$0.4 V, $V_{\rm GS}$ $=$ 0 V) and ON-state ($V_{\rm DS}$ $=$ 0.4 V, $V_{\rm GS}$ $=$ 0.4 V) at the channel and dielectric interface (top).

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Fig. 6.  Recombination rate of GaSb/InAs JLTFET as a function of position along the $x$-direction in the OFF-state ($V_{\rm DS}$ $=$ 0.4 V, $V_{\rm GS}$ $=$ 0 V) and ON-state ($V_{\rm DS}$ $=$ 0.4 V, $V_{\rm GS}$ $=$ 0.4 V) at the channel and dielectric interface (top).

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Fig. 7.  Drain current versus gate voltage of GaSb/InAs JLTFET at a drain voltage of 0.01 to 0.4 V.

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Fig. 8.  Transconductance $G_{\rm m}$ versus $V_{\rm GS}$ of GaSb/InAs JLTFET at $V_{\rm DS}$ from 0.01 to 0.4 V.

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Fig. 9.  Output characteristics and output transconductance with respect to drain voltage for GaSb/InAs JLTFET at gate voltages of 0.3 and 0.4 V.

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Fig. 10.  Variation of capacitances, $C_{\rm GD}$ and $C_{\rm GS}$, in GaSb/InAs JLTFET with the gate voltage at $V_{\rm DS}$ $=$ 0.4 V, a small signal voltage of 5 mV and a frequency of 1 MHz.

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    Received: 20 July 2014 Revised: Online: Published: 01 February 2015

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      Article Navigation >  Journal of Semiconductors  > 2015  >  36(2): 024003
      Pranav Kumar Asthana. High performance 20 nm GaSb/InAs junctionless tunnel field effect transistor for low power supply[J]. Journal of Semiconductors, 2015, 36(2): 024003. doi: 10.1088/1674-4926/36/2/024003 ****P K Asthana. High performance 20 nm GaSb/InAs junctionless tunnel field effect transistor for low power supply[J]. J. Semicond., 2015, 36(2): 024003. doi: 10.1088/1674-4926/36/2/024003.
      Citation:
      Pranav Kumar Asthana. High performance 20 nm GaSb/InAs junctionless tunnel field effect transistor for low power supply[J]. Journal of Semiconductors, 2015, 36(2): 024003. doi: 10.1088/1674-4926/36/2/024003 ****
      P K Asthana. High performance 20 nm GaSb/InAs junctionless tunnel field effect transistor for low power supply[J]. J. Semicond., 2015, 36(2): 024003. doi: 10.1088/1674-4926/36/2/024003.
      shu

      High performance 20 nm GaSb/InAs junctionless tunnel field effect transistor for low power supply

      DOI: 10.1088/1674-4926/36/2/024003

      • Department of Electrical Engineering, Indian Institute of Technology Kanpur, Kanpur 208016, India

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      • Corresponding author: E-mail: pranavasthana32@gmail.com
      • Received Date: 2014-07-20
      • Published Date: 2015-01-25

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