J. Semicond. > 2015, Volume 36 > Issue 6 > Article Number: 065008

14-bit 100 MS/s 121 mW pipelined ADC

Yongzhen Chen , Chixiao Chen , Zemin Feng , Fan Ye and Junyan Ren ,

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Abstract: This paper presents a high-speed high-resolution pipelined ADC with low power and small area. The proposed ADC is designed based on the analysis of the stage scaling theory and the residual amplifiers are shared by two cascading MDACs to reduce power consumption. Shared op-amps with two split input paths are presented in this paper to eliminate the nonlinearity effects such as memory effect and crosstalk. Dynamic pre-amplified comparators are employed to decrease the static power consumption and suppress the kick-back in the comparators. This ADC is implemented in SMIC 0.18 μm CMOS process with an area of 3.1 mm2. With a sampling rate of 100 MS/s, spurious-free dynamic range (SFDR) and signal-to-noise plus distortion ratio (SNDR) of the ADC are 82.7 dB and 69.1 dB, respectively. For signals up to 100 MHz, the SFDR and SNDR achieve 81.4 dB and 65.8 dB. The power consumption is 121 mW with a 1.8 V supply voltage.

Key words: ADCpipelinelow powerstage scalingop-amp sharingcomparator



References:

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Cai Hua, Li Ping, Cen Yuanjun. A 14-bit 80 MS/s CMOS ADC with 84.8 dB SFDR and 72 dB SNDR[J]. Journal of Semiconductors, 2012, 33(2)-025012.

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Wang Ke, Fan Chaojie, Zhou Jianjun. A 14-bit 100-MS/s CMOS pipelined ADC with 11.3 ENOB[J]. Journal of Semiconductors, 2013, 34(8)-085015.

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Van de Vel H, Buter B A J, van der Ploeg H. A 1.2-V 250-mW 14-b 100-MS/s digitally calibrated pipeline ADC in 90-nm CMOS[J]. IEEE J Solid State Circuits, 2009, 44(4): 1047.

[1]

Lee K H, Lee S W, Kim Y J. Ten-bit 100 MS/s 24.2 mW 0.8 mm2 0.18 μm CMOS pipeline ADC based on maximal circuit sharing schemes[J]. Electron Lett, 2009, 45(25): 1296.

[2]

Wang Z, Wang M, Gu W. A high-linearity pipelined ADC with opamp split-sharing in a combined front-end of S/H and MDAC1[J]. IEEE Trans Circuits Syst I, Reg Papers, 2013: 2834.

[3]

Yang C, Li F, Li W. An 85 mW 14-bit 150 MS/s pipelined ADC with 71.3 dB peak SNDR in 130 nm CMOS[J]. IEEE Asian Solid-State Circuits Conference, 2013: 85.

[4]

Devarajan S, Singer L, Kelly D. A 16-bit, 125 MS/s, 385 mW, 78.7 dB SNR CMOS pipeline ADC[J]. IEEE J Solid-State Circuits, 2009, 44(12): 3305.

[5]

Cline D W, Gray P R. A power optimized 13-bit 5 M samples/s pipelined analog to digital converter in 1.2 μm CMOS[J]. IEEE Proc CICC, 1995: 219.

[6]

Cheng L, Yang H, Luo L. Analysis and design of low jitter clock driver for wideband ADC[J]. Proc ICSICT, 2010: 515.

[7]

Cai Hua, Li Ping, Cen Yuanjun. A 14-bit 80 MS/s CMOS ADC with 84.8 dB SFDR and 72 dB SNDR[J]. Journal of Semiconductors, 2012, 33(2)-025012.

[8]

Wang Ke, Fan Chaojie, Zhou Jianjun. A 14-bit 100-MS/s CMOS pipelined ADC with 11.3 ENOB[J]. Journal of Semiconductors, 2013, 34(8)-085015.

[9]

Van de Vel H, Buter B A J, van der Ploeg H. A 1.2-V 250-mW 14-b 100-MS/s digitally calibrated pipeline ADC in 90-nm CMOS[J]. IEEE J Solid State Circuits, 2009, 44(4): 1047.

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Y Z Chen, C X Chen, Z M Feng, F Ye, J Y Ren. 14-bit 100 MS/s 121 mW pipelined ADC[J]. J. Semicond., 2015, 36(6): 065008. doi: 10.1088/1674-4926/36/6/065008.

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History

Manuscript received: 03 November 2014 Manuscript revised: Online: Published: 01 June 2015

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