J. Semicond. > Volume 36 > Issue 6 > Article Number: 065008

14-bit 100 MS/s 121 mW pipelined ADC

Yongzhen Chen , Chixiao Chen , Zemin Feng , Fan Ye and Junyan Ren ,

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Abstract: This paper presents a high-speed high-resolution pipelined ADC with low power and small area. The proposed ADC is designed based on the analysis of the stage scaling theory and the residual amplifiers are shared by two cascading MDACs to reduce power consumption. Shared op-amps with two split input paths are presented in this paper to eliminate the nonlinearity effects such as memory effect and crosstalk. Dynamic pre-amplified comparators are employed to decrease the static power consumption and suppress the kick-back in the comparators. This ADC is implemented in SMIC 0.18 μm CMOS process with an area of 3.1 mm2. With a sampling rate of 100 MS/s, spurious-free dynamic range (SFDR) and signal-to-noise plus distortion ratio (SNDR) of the ADC are 82.7 dB and 69.1 dB, respectively. For signals up to 100 MHz, the SFDR and SNDR achieve 81.4 dB and 65.8 dB. The power consumption is 121 mW with a 1.8 V supply voltage.

Key words: ADCpipelinelow powerstage scalingop-amp sharingcomparator

Abstract: This paper presents a high-speed high-resolution pipelined ADC with low power and small area. The proposed ADC is designed based on the analysis of the stage scaling theory and the residual amplifiers are shared by two cascading MDACs to reduce power consumption. Shared op-amps with two split input paths are presented in this paper to eliminate the nonlinearity effects such as memory effect and crosstalk. Dynamic pre-amplified comparators are employed to decrease the static power consumption and suppress the kick-back in the comparators. This ADC is implemented in SMIC 0.18 μm CMOS process with an area of 3.1 mm2. With a sampling rate of 100 MS/s, spurious-free dynamic range (SFDR) and signal-to-noise plus distortion ratio (SNDR) of the ADC are 82.7 dB and 69.1 dB, respectively. For signals up to 100 MHz, the SFDR and SNDR achieve 81.4 dB and 65.8 dB. The power consumption is 121 mW with a 1.8 V supply voltage.

Key words: ADCpipelinelow powerstage scalingop-amp sharingcomparator



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Wang Z, Wang M, Gu W. A high-linearity pipelined ADC with opamp split-sharing in a combined front-end of S/H and MDAC1[J]. IEEE Trans Circuits Syst I, Reg Papers, 2013: 2834.

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Y Z Chen, C X Chen, Z M Feng, F Ye, J Y Ren. 14-bit 100 MS/s 121 mW pipelined ADC[J]. J. Semicond., 2015, 36(6): 065008. doi: 10.1088/1674-4926/36/6/065008.

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Manuscript received: 03 November 2014 Manuscript revised: Online: Published: 01 June 2015

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