J. Semicond. > Volume 36 > Issue 8 > Article Number: 085006

An efficient method for comprehensive modeling and parasitic extraction of cylindrical through-silicon vias in 3D ICs

Qiang Yao 1, , Zuochang Ye 1, and Wenjian Yu 2, ,

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Abstract: To build an accurate electric model for through-silicon vias (TSVs) in 3D integrated circuits (ICs), a resistance and capacitance (RC) circuit model and related efficient extraction technique are proposed. The circuit model takes both semiconductor and electrostatic effects into account, and is valid for low and medium signal frequencies. The electrostatic capacitances are extracted with a floating random walk based algorithm, and are then combined with the voltage-dependent semiconductor capacitances to form the equivalent circuit. Compared with the method used in Synopsys's Sdevice, which completely simulates the electro/semiconductor effects, the proposed method is more efficient and is able to handle the general TSV layout as well. For several TSV structures, the experimental results validate the accuracy of the proposed method for the frequency range from 10 kHz to 1 GHz. The proposed method demonstrated 47× speedup over the Sdevice for the largest 9-TSV case.

Key words: 3D ICthrough silicon via (TSV)parasitic extractionfloating random walk algorithmmetal-oxide-semiconductor (MOS) capacitance

Abstract: To build an accurate electric model for through-silicon vias (TSVs) in 3D integrated circuits (ICs), a resistance and capacitance (RC) circuit model and related efficient extraction technique are proposed. The circuit model takes both semiconductor and electrostatic effects into account, and is valid for low and medium signal frequencies. The electrostatic capacitances are extracted with a floating random walk based algorithm, and are then combined with the voltage-dependent semiconductor capacitances to form the equivalent circuit. Compared with the method used in Synopsys's Sdevice, which completely simulates the electro/semiconductor effects, the proposed method is more efficient and is able to handle the general TSV layout as well. For several TSV structures, the experimental results validate the accuracy of the proposed method for the frequency range from 10 kHz to 1 GHz. The proposed method demonstrated 47× speedup over the Sdevice for the largest 9-TSV case.

Key words: 3D ICthrough silicon via (TSV)parasitic extractionfloating random walk algorithmmetal-oxide-semiconductor (MOS) capacitance



References:

[1]

Synopsys Inc. Sentaurus device user guide[J]. , 2008(09).

[2]

Katti G, Stucchi M, De Meyer K. Electrical modeling and characterization of through silicon via for three-dimensional ICs[J]. IEEE Trans Electron Devices, 2010, 57(1): 256.

[3]

Liu C, Song T, Cho J. Full-chip TSV-to-TSV coupling analysis and optimization in 3D IC[J]. Proc Design Automation Conference (DAC), 2011: 783.

[4]

Savidis I, Friedman E G. Closed-form expressions of 3-D via resistance, inductance, and capacitance[J]. IEEE Trans Electron Devices, 2009, 56(9): 1873.

[5]

Kim D H, Mukhopadhyay S, Lim S K. Fast and accurate analytical modeling of through-silicon-via capacitive coupling[J]. IEEE Trans Components, Packaging and Manufacturing Technology, 2011, 1(2): 168.

[6]

Chang Y J, Chuang H H, Lu Y C. Novel crosstalk modeling for multiple through-silicon-vias (TSV) on 3-D IC: experimental validation and application to Faraday cage design[J]. Proc International Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), 2012: 232.

[7]

Peng Y, Petranovic D, Lim S K. Fast and accurate full-chip extraction and optimization of TSV-to-wire coupling[J]. Proc Design Automation Conference (DAC), San Francisco, 2014: 1.

[8]

Yu W, Zhang C, Wang Q. Random walk based capacitance extraction for 3D ICs with cylindrical inter-tier vias[J]. Proc International Conference on Computer-Aided Design (ICCAD), San Jose, 2014: 702.

[9]

Sze S M. Physics of semiconductor devices[J]. New York: Wiley, 1981.

[10]

Yu W, Zhuang H, Zhang C. RWCap: a floating random walk solver for 3-D capacitance extraction of VLSI interconnects[J]. IEEE Trans Computer-Aided Design, 2013, 32: 353.

[11]

Yu W, Wang X. Advanced field-solver techniques for RC extraction of integrated circuits[J]. Springer Inc, 2014.

[12]

Nabors, White. J Fastcap: a multipole accelerated 3-D capacitance extraction program[J]. IEEE Trans Computer-Aided Design, 1991, 10(11): 1447.

[1]

Synopsys Inc. Sentaurus device user guide[J]. , 2008(09).

[2]

Katti G, Stucchi M, De Meyer K. Electrical modeling and characterization of through silicon via for three-dimensional ICs[J]. IEEE Trans Electron Devices, 2010, 57(1): 256.

[3]

Liu C, Song T, Cho J. Full-chip TSV-to-TSV coupling analysis and optimization in 3D IC[J]. Proc Design Automation Conference (DAC), 2011: 783.

[4]

Savidis I, Friedman E G. Closed-form expressions of 3-D via resistance, inductance, and capacitance[J]. IEEE Trans Electron Devices, 2009, 56(9): 1873.

[5]

Kim D H, Mukhopadhyay S, Lim S K. Fast and accurate analytical modeling of through-silicon-via capacitive coupling[J]. IEEE Trans Components, Packaging and Manufacturing Technology, 2011, 1(2): 168.

[6]

Chang Y J, Chuang H H, Lu Y C. Novel crosstalk modeling for multiple through-silicon-vias (TSV) on 3-D IC: experimental validation and application to Faraday cage design[J]. Proc International Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), 2012: 232.

[7]

Peng Y, Petranovic D, Lim S K. Fast and accurate full-chip extraction and optimization of TSV-to-wire coupling[J]. Proc Design Automation Conference (DAC), San Francisco, 2014: 1.

[8]

Yu W, Zhang C, Wang Q. Random walk based capacitance extraction for 3D ICs with cylindrical inter-tier vias[J]. Proc International Conference on Computer-Aided Design (ICCAD), San Jose, 2014: 702.

[9]

Sze S M. Physics of semiconductor devices[J]. New York: Wiley, 1981.

[10]

Yu W, Zhuang H, Zhang C. RWCap: a floating random walk solver for 3-D capacitance extraction of VLSI interconnects[J]. IEEE Trans Computer-Aided Design, 2013, 32: 353.

[11]

Yu W, Wang X. Advanced field-solver techniques for RC extraction of integrated circuits[J]. Springer Inc, 2014.

[12]

Nabors, White. J Fastcap: a multipole accelerated 3-D capacitance extraction program[J]. IEEE Trans Computer-Aided Design, 1991, 10(11): 1447.

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Q Yao, Z C Ye, W J Yu. An efficient method for comprehensive modeling and parasitic extraction of cylindrical through-silicon vias in 3D ICs[J]. J. Semicond., 2015, 36(8): 085006. doi: 10.1088/1674-4926/36/8/085006.

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Manuscript received: 01 February 2015 Manuscript revised: Online: Published: 01 August 2015

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