J. Semicond. > Volume 36 > Issue 8 > Article Number: 085007

A low power 12-bit 1 Msps successive approximation register ADC with an improved switching procedure

Fubin Xin 1, 2, , Tao Yin 1, , Qisong Wu 1, , Yuanlong Yang 1, 2, , Fei Liu 1, and Haigang Yang 1, ,

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Abstract: As a key building block of data acquisition systems, power dissipation of the successive approximation register (SAR) ADC determines the total power consumption of the system. In this paper, a low power 12-bit 1 Msps SAR ADC with an improved switching procedure is presented. Power consumption and area occupation could be significantly reduced by using the proposed switching procedure. Compared to converters that use the conventional switching procedure, the average switching energy could be reduced by about 80% and the total capacitance could be reduced by 50%. A simplified digital control logic is utilized to reduce power dissipation and area occupation of the digital control circuits. Simulation results show that the power dissipated by the proposed digital control circuits could be reduced by about 50% compared to the power dissipated by conventional control circuits. The chip has been processed in a standard 0.35μm CMOS technology and has a core die area of 1.12 mm2. A signal-to-noise-and-distortion-ratio of 64.2 dB has been measured with a 100 kHz signal input under a wide range variation of temperature from -55 to 150 ℃. The total power consumption of the prototype is only 0.72 mW with a 3.3 V supply voltage.

Key words: analog to digital converterSARlow powerCMOSeffective number of bits

Abstract: As a key building block of data acquisition systems, power dissipation of the successive approximation register (SAR) ADC determines the total power consumption of the system. In this paper, a low power 12-bit 1 Msps SAR ADC with an improved switching procedure is presented. Power consumption and area occupation could be significantly reduced by using the proposed switching procedure. Compared to converters that use the conventional switching procedure, the average switching energy could be reduced by about 80% and the total capacitance could be reduced by 50%. A simplified digital control logic is utilized to reduce power dissipation and area occupation of the digital control circuits. Simulation results show that the power dissipated by the proposed digital control circuits could be reduced by about 50% compared to the power dissipated by conventional control circuits. The chip has been processed in a standard 0.35μm CMOS technology and has a core die area of 1.12 mm2. A signal-to-noise-and-distortion-ratio of 64.2 dB has been measured with a 100 kHz signal input under a wide range variation of temperature from -55 to 150 ℃. The total power consumption of the prototype is only 0.72 mW with a 3.3 V supply voltage.

Key words: analog to digital converterSARlow powerCMOSeffective number of bits



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Agnes A, Bonizzoni E, Malcovati P. A 9[J]. IEEE International Solid-State Circuits Conference, Digest of Technical Papers, 2008: 246.

[2]

Liu C C, Chang S J, Huang G Y. A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure[J]. IEEE J Solid-State Circuits, 2010, 45(4): 731.

[3]

Zhu Y, Chan C H, Chio U F. A 10-bit 100-MS/s reference-free SAR ADC in 90 nm CMOS[J]. IEEE J Solid-State Circuits, 2010, 45(5): 1111.

[4]

Zhu Zhangming, Xiao Yu, Song Xiaoli. VCM-based monotonic capacitor switching scheme for SAR ADC[J]. Electron Lett, 2013, 49(5): 327.

[5]

Zhu Zhangming, Qiu Zheng, Liu Maliang. A 6-to-10-bit 0[J]. IEEE Trans Circuits Syst I, 2012, 59(1): 80.

[6]

Tong Xingyuan, Chen Jianming, Zhu Zhangming. A high performance 90 nm CMOS SAR ADC with hybrid architecture[J]. Journal of Semiconductors, 2010, 31(1): 015002.

[7]

Zhu Y, Chan C H, Chio U F. Parasitics nonlinearity cancellation technique for split DAC architecture by using capacitive charge-pump[J]. IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), 2010: 889.

[8]

Doris K, Janssen E, Nani C. A 480 mW 2[J]. IEEE J Solid-State Circuits, 2011, 46(12): 2821.

[9]

Verbruggen B, Iriguchi M, Craninckx J. A 1[J]. IEEE J Solid-State Circuits, 2012, 47(12): 2880.

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Furuta M, Nozawa M, Itakura T. A 10-bit, 40-MS/s, 1[J]. IEEE J Solid-State Circuits, 2011, 46(6): 1360.

[11]

Promitzer G. 12-bit low-power fully differential switched capacitor noncalibrating successive approximation ADC with 1 MS/s[J]. IEEE J Solid-State Circuits, 2001, 36(7): 1138.

[12]

Yang Siyu, Zhang Hui, Fu Wenhui. A low power 12-bit 200-kS/s SAR ADC with a differential time domain comparator[J]. Journal of Semiconductors, 2011, 32(3): 035002.

[13]

Wang Z, Lin R, Gordon E. An in-situ temperature-sensing interface based on a SAR ADC in 45 nm LP digital CMOS for the frequency-temperature compensation of crystal oscillators[J]. IEEE International Solid-State Circuits Conference, 2010: 316.

[14]

Agnes A, Bonizzoni E, Maicovati P. A 9[J]. IEEE International Solid-State Circuits Conference (ISSCC), 2008(51): 246.

[15]

Fan Hua, Han Xue, Wei Qi. An 11-bit ENOB, accuracy-programmable, and non-calibrating time-mode SAR ADC[J]. Journal of Semiconductors, 2013, 34(1): 015010.

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F B Xin, T Yin, Q S Wu, Y L Yang, F Liu, H G Yang. A low power 12-bit 1 Msps successive approximation register ADC with an improved switching procedure[J]. J. Semicond., 2015, 36(8): 085007. doi: 10.1088/1674-4926/36/8/085007.

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Manuscript received: 03 February 2015 Manuscript revised: Online: Published: 01 August 2015

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