J. Semicond. > Volume 36 > Issue 8 > Article Number: 085008

A 10-bit 120-MS/s pipelined ADC with improved switch and layout scaling strategy

Jia Zhou 1, 2, , , Lili Xu 1, 2, , Fule Li 1, 2, and Zhihua Wang 1, 2,

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Abstract: A 10 bit, 120 MS/s two-channel pipelined analog-to digital converter (ADC) is presented. The ADC is featured with improved switch by using the body effect to improve its conduction performance. A scaling down strategy is proposed to get more efficiency in the OTA's layout design. Implemented in a 0.18-μ m CMOS technology, the ADC's prototype occupied an area of 2.05 × 1.83 mm2. With a sampling rate of 120-MS/s and an input of 4.9 MHz, the ADC achieves a spurious-free-dynamic range of 74.32 dB and signal-to-noise-and-distortion ratio of 55.34 dB, while consuming 220-mW/channel at 3-V supply.

Key words: ADCpipelinebody-effectscaling downparallel

Abstract: A 10 bit, 120 MS/s two-channel pipelined analog-to digital converter (ADC) is presented. The ADC is featured with improved switch by using the body effect to improve its conduction performance. A scaling down strategy is proposed to get more efficiency in the OTA's layout design. Implemented in a 0.18-μ m CMOS technology, the ADC's prototype occupied an area of 2.05 × 1.83 mm2. With a sampling rate of 120-MS/s and an input of 4.9 MHz, the ADC achieves a spurious-free-dynamic range of 74.32 dB and signal-to-noise-and-distortion ratio of 55.34 dB, while consuming 220-mW/channel at 3-V supply.

Key words: ADCpipelinebody-effectscaling downparallel



References:

[1]

Liechti T, Tajalli A, Akgun O C. A 1[J]. IEEE Asia Pacific Conference on Circuits and Systems, 2008: 21.

[2]

Ahmed I. Pipelined ADC design and enhancement techniques[J]. Springer, 2010.

[3]

Amirabadi A, Tabrizi M M, Sharifkhani M. A 10 b, 40 Msample/s, 25 mW pipeline analog to digital converter[J]. IEEE Canadian Conference on Electrical and Computer Engineering, 2004, 4: 1989.

[4]

Diaz-Madrid J A, Neubauer H, Hauer H. Power reduction of a 12-bit 40-MS/s pipeline ADC exploiting partial amplifier sharing[J]. Proceedings of the Conference on Design, Automation and Test in Europe, European Design and Automation Association, 2009: 369.

[5]

Kwok P T F, Luong H C. Power optimization for pipeline analog-to-digital converters[J]. IEEE Trans Circuits Syst II: Analog and Digital Signal Processing, 1999, 46(5): 549.

[6]

Li B, Li Z, Li Y. A 57 mW 10-bit 80-MS/s pipeline ADC adopting improved power optimization approach[J]. IEEE 7th International Conference on ASIC, 2007: 616.

[7]

Min B M, Kim P, Bowman III F W. A 69-mW 10-bit 80-MSample/s pipelined CMOS ADC[J]. IEEE J Solid-State Circuits, 2003, 38(12): 2031.

[8]
[1]

Liechti T, Tajalli A, Akgun O C. A 1[J]. IEEE Asia Pacific Conference on Circuits and Systems, 2008: 21.

[2]

Ahmed I. Pipelined ADC design and enhancement techniques[J]. Springer, 2010.

[3]

Amirabadi A, Tabrizi M M, Sharifkhani M. A 10 b, 40 Msample/s, 25 mW pipeline analog to digital converter[J]. IEEE Canadian Conference on Electrical and Computer Engineering, 2004, 4: 1989.

[4]

Diaz-Madrid J A, Neubauer H, Hauer H. Power reduction of a 12-bit 40-MS/s pipeline ADC exploiting partial amplifier sharing[J]. Proceedings of the Conference on Design, Automation and Test in Europe, European Design and Automation Association, 2009: 369.

[5]

Kwok P T F, Luong H C. Power optimization for pipeline analog-to-digital converters[J]. IEEE Trans Circuits Syst II: Analog and Digital Signal Processing, 1999, 46(5): 549.

[6]

Li B, Li Z, Li Y. A 57 mW 10-bit 80-MS/s pipeline ADC adopting improved power optimization approach[J]. IEEE 7th International Conference on ASIC, 2007: 616.

[7]

Min B M, Kim P, Bowman III F W. A 69-mW 10-bit 80-MSample/s pipelined CMOS ADC[J]. IEEE J Solid-State Circuits, 2003, 38(12): 2031.

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J Zhou, L L Xu, F L Li, Z H Wang. A 10-bit 120-MS/s pipelined ADC with improved switch and layout scaling strategy[J]. J. Semicond., 2015, 36(8): 085008. doi: 10.1088/1674-4926/36/8/085008.

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Manuscript received: 20 January 2015 Manuscript revised: Online: Published: 01 August 2015

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