Y Q Mao, T Q Gao, X D Xu, H G Yang, X X Cai. A fully integrated CMOS super-regenerative wake-up receiver for EEG applications[J]. J. Semicond., 2016, 37(9): 095001. doi: 10.1088/1674-4926/37/9/095001.
Yiqi Mao 1, 2, , Tongqiang Gao 1, 2, , Xiaodong Xu 1, , Haigang Yang 1, 2, , and Xinxia Cai 1, 2,
Abstract: A fully integrated super-regenerative wake-up receiver for wireless body area network applications is presented. The super-regeneration receiver is designed to receive OOK-modulated data from the base station. A low power waveform generator is adopted both to provide a quench signal for VCO and to provide a clock signal for the digital module. The receiver is manufactured in 0.18 μm CMOS process and the active area is 0.67 mm2. It achieves a sensitivity of -80 dBm for 10-3 BER with a data rate of 200 kbps. The power consumption of the super-regenerative wake-up receiver is about 2.16 mW.
Key words: super-regenerative receiver, wake-up circuit, EEG, OOK, CMOS
Abstract: A fully integrated super-regenerative wake-up receiver for wireless body area network applications is presented. The super-regeneration receiver is designed to receive OOK-modulated data from the base station. A low power waveform generator is adopted both to provide a quench signal for VCO and to provide a clock signal for the digital module. The receiver is manufactured in 0.18 μm CMOS process and the active area is 0.67 mm2. It achieves a sensitivity of -80 dBm for 10-3 BER with a data rate of 200 kbps. The power consumption of the super-regenerative wake-up receiver is about 2.16 mW.
Key words:
super-regenerative receiver, wake-up circuit, EEG, OOK, CMOS
References:
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Favre P, Joehl N, Vouilloz A. A 2-V 600-μ A 1-GHz BiCMOS super-regenerative receiver for ISM application[J]. IEEE J Solid-State Circuit, 1998, 33(12): 2186. doi: 10.1109/4.735703 |
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Chen J Y, Flynn M P, Hayes J P. A fully integrated auto-calibrated super-regenerative receiver in 0.13-μm CMOS[J]. IEEE J Solid-State Circuits, 2007, 42(9): 1976. doi: 10.1109/JSSC.2007.903092 |
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Meyer R. Low-power monolithic RF peak detector analysis[J]. IEEE J Solid State Circuits, 1995, 30(1): 65. doi: 10.1109/4.350192 |
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Rabaey J M, Chandrakasam A, Nikolic B. Digital integrated circuits: a design perspective. 2nd ed. Electronics & VLSI, 2002 |
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Chen J Y. Design of low-power super-regenerative receivers. The University of Michigan, 2006 |
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Barner R, Liu J. A 0.8 V 1.52 MHz MSVC relaxation oscillator with inverted mirror feedback reference for UHF RFID. IEEE Custom Integrated Circuits Conference (CICC), 2006: 769 |
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Harrison R R, Charles C. A low-power low-noise CMOS amplifier for neural recording applications[J]. IEEE J Solid-State Circuits, 2003, 38(6): 958. doi: 10.1109/JSSC.2003.811979 |
[11] |
Zhu Wenrui, Yang Haigang, Gao Tongqiang. A baseband circuit for wake-up receivers with double-mode detection and enhanced sensitivity robustness[J]. Journal of Semiconductors, 2013, 34(8): 085011. doi: 10.1088/1674-4926/34/8/085011 |
[12] |
Liu Y H, Lin T H. A delta-sigma pulse-width digitization technique for super-regenerative receivers[J]. IEEE J Solid State-Circuits, 2010, 45(10): 2066. doi: 10.1109/JSSC.2010.2061614 |
[1] |
Armstrong E H. Some recent developments of regenerative circuits[J]. Proceedings of the Institute of Radio Engineers, 1922, 10(4): 244. |
[2] |
Favre P, Joehl N, Vouilloz A. A 2-V 600-μ A 1-GHz BiCMOS super-regenerative receiver for ISM application[J]. IEEE J Solid-State Circuit, 1998, 33(12): 2186. doi: 10.1109/4.735703 |
[3] |
Zahabi A, Anis M, Ortmanns M. 2.4 GHz super-regeneration amplifier with degenerative quenching technique for RF-pulse width transceiver. IEEE International Symposium on Circuits and System (ISCAS), 2012: 2147 |
[4] |
Otis B, Chee Y H, Rabaey J. A 400μ W-RX, 1.6 mW-TX super-regenerative transceiver for wireless sensor networks. Solid-State Circuits Conference (ISSCC), 2005, 1: 396 |
[5] |
Chen J Y, Flynn M P, Hayes J P. A fully integrated auto-calibrated super-regenerative receiver in 0.13-μm CMOS[J]. IEEE J Solid-State Circuits, 2007, 42(9): 1976. doi: 10.1109/JSSC.2007.903092 |
[6] |
Meyer R. Low-power monolithic RF peak detector analysis[J]. IEEE J Solid State Circuits, 1995, 30(1): 65. doi: 10.1109/4.350192 |
[7] |
Rabaey J M, Chandrakasam A, Nikolic B. Digital integrated circuits: a design perspective. 2nd ed. Electronics & VLSI, 2002 |
[8] |
Chen J Y. Design of low-power super-regenerative receivers. The University of Michigan, 2006 |
[9] |
Barner R, Liu J. A 0.8 V 1.52 MHz MSVC relaxation oscillator with inverted mirror feedback reference for UHF RFID. IEEE Custom Integrated Circuits Conference (CICC), 2006: 769 |
[10] |
Harrison R R, Charles C. A low-power low-noise CMOS amplifier for neural recording applications[J]. IEEE J Solid-State Circuits, 2003, 38(6): 958. doi: 10.1109/JSSC.2003.811979 |
[11] |
Zhu Wenrui, Yang Haigang, Gao Tongqiang. A baseband circuit for wake-up receivers with double-mode detection and enhanced sensitivity robustness[J]. Journal of Semiconductors, 2013, 34(8): 085011. doi: 10.1088/1674-4926/34/8/085011 |
[12] |
Liu Y H, Lin T H. A delta-sigma pulse-width digitization technique for super-regenerative receivers[J]. IEEE J Solid State-Circuits, 2010, 45(10): 2066. doi: 10.1109/JSSC.2010.2061614 |
Y Q Mao, T Q Gao, X D Xu, H G Yang, X X Cai. A fully integrated CMOS super-regenerative wake-up receiver for EEG applications[J]. J. Semicond., 2016, 37(9): 095001. doi: 10.1088/1674-4926/37/9/095001.
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Manuscript received: 04 January 2016 Manuscript revised: 12 April 2016 Online: Published: 01 September 2016
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