J. Semicond. > 2017, Volume 38 > Issue 8 > Article Number: 085005

An 8 bit 1 MS/s SAR ADC with 7.72-ENOB

Jihai Duan , , Zhiyong Zhu , Jinli Deng and Weilin Xu

+ Author Affiliations + Find other works by these authors
  • Corresponding author: Jihai Duan, Jihai Duan, Email:drdjh98@163.com
  • PDF

    Abstract: This paper presents a low power 8-bit 1 MS/s SAR ADC with 7.72-bit ENOB. Without an op-amp, an improved segmented capacitor DAC is proposed to reduce the capacitance and the chip area. A dynamic latch comparator with output offset voltage storage technology is used to improve the precision. Adding an extra positive feedback in the latch is to increase the speed. What is more, two pairs of CMOS switches are utilized to eliminate the kickback noise introduced by the latch. The proposed SAR ADC was fabricated in SMIC 0.18 μm CMOS technology. The measured results show that this design achieves an SFDR of 61.8 dB and an ENOB of 7.72 bits, and it consumes 67.5 μ W with the FOM of 312 fJ/conversion-step at 1 MS/s sample under 1.8 V power supply.

    Key words: SAR ADCdynamic latch comparatoroutput offset voltage storage technologykickback noise



    References:

    [1]

    Ginsburg B P, Chandrakasan A P. Highly interleaved 5-bit, 250-MSample/s, 1.2-mW ADC with redundant channels in 65-nm CMOS[J]. IEEE J Solid-State Circuits, 2008, 43(12): 2641. doi: 10.1109/JSSC.2008.2006334

    [2]

    Cao T V, Aunet S, Ytterdal T. A 9-bit 50MS/s asynchronous SAR ADC in 28 nm CMOS[J]. Norchip, 2012: 1.

    [3]

    Zhang H, Qin Y J, Yang S Y. A 455 nW 220 fJ/conversion-step 12 bits 2 kS/s SAR ADC for portable biopotential acquisition systems[J]. J Semicond, 2011, 32(1): 79.

    [4]

    Shen Y, Liu S, Zhu Z. A 12-bit 50MS/s zero-crossing-based two-stage pipelined SAR ADC in 0.18μm CMOS[J]. Microelectron J, 2016, 57: 26. doi: 10.1016/j.mejo.2016.09.002

    [5]

    Muratore D G, Bonizzoni E, Maloberti F. A split transconductor high-speed SAR ADC[J]. IEEE International Symposium on Circuits and Systems, 2015: 2433.

    [6]

    Liu W, Wei T, Guo P. Design of a novel 12-bit 1MS/s charge redistribution SAR ADC for CZT detectors[J]. IEEE Conference on Industrial Electronics and Applications, 2014: 867.

    [7]

    Hu W, Liu Y T, Nguyen T. An 8-bit single-ended ultra-low-power SAR ADC with a novel DAC switching method and a counter-based digital control circuitry[J]. IEEE Trans Circuits Syst I, 2013, 60(7): 1726. doi: 10.1109/TCSI.2012.2230587

    [8]

    Van d P G, Decoutere S, Donnay S. A 0.16 pJ/conversion-step 2.5 mW 1.25 GS/s 4 b ADC in a 90 nm digital CMOS process[J]. IEEE International Solid-State Circuits Conference (ISSCC), 2006: 2310.

    [9]

    Das I, Sahoo M, Roy P. A 45μW 13 pJ/conv-step 7.4-ENOB 40 kS/s SAR ADC for digital microfluidic biochip applications[J]. International Symposium on VlSI Design and Test, 2014: 1.

    [10]

    Shrivastava P, Bhat K G, Laxminidhi T. A 500 kS/s 8-bit charge recycle based 2-bit per step SAR-ADC[J]. Third International Conference on Emerging Applications of Information Technology, 2012: 462.

    [11]

    Nazzal T B, Mahmoud S A, Shaker M O. A 200-nW 7.6-ENOB 10-KS/s SAR ADC in 90-nm CMOS for Portable Biomedical Applications[J]. Microelectronics J, 2016, 56: 81. doi: 10.1016/j.mejo.2016.08.004

    [12]

    Mahmoud S A. An 8-bit, 10 kS/s, 1. 87μW successive approximation analog to digital converter in 0. 25μm CMOS technology for ECG detection systems. Circuits Systems & Signal Processing, 2015

    [13]

    Liu L Y, Li D M, Chen L D. A low power 8-bit successive approximation register A/D for a wireless body sensor node[J]. J Semicond, 2010, 31(6): 93.

    [1]

    Ginsburg B P, Chandrakasan A P. Highly interleaved 5-bit, 250-MSample/s, 1.2-mW ADC with redundant channels in 65-nm CMOS[J]. IEEE J Solid-State Circuits, 2008, 43(12): 2641. doi: 10.1109/JSSC.2008.2006334

    [2]

    Cao T V, Aunet S, Ytterdal T. A 9-bit 50MS/s asynchronous SAR ADC in 28 nm CMOS[J]. Norchip, 2012: 1.

    [3]

    Zhang H, Qin Y J, Yang S Y. A 455 nW 220 fJ/conversion-step 12 bits 2 kS/s SAR ADC for portable biopotential acquisition systems[J]. J Semicond, 2011, 32(1): 79.

    [4]

    Shen Y, Liu S, Zhu Z. A 12-bit 50MS/s zero-crossing-based two-stage pipelined SAR ADC in 0.18μm CMOS[J]. Microelectron J, 2016, 57: 26. doi: 10.1016/j.mejo.2016.09.002

    [5]

    Muratore D G, Bonizzoni E, Maloberti F. A split transconductor high-speed SAR ADC[J]. IEEE International Symposium on Circuits and Systems, 2015: 2433.

    [6]

    Liu W, Wei T, Guo P. Design of a novel 12-bit 1MS/s charge redistribution SAR ADC for CZT detectors[J]. IEEE Conference on Industrial Electronics and Applications, 2014: 867.

    [7]

    Hu W, Liu Y T, Nguyen T. An 8-bit single-ended ultra-low-power SAR ADC with a novel DAC switching method and a counter-based digital control circuitry[J]. IEEE Trans Circuits Syst I, 2013, 60(7): 1726. doi: 10.1109/TCSI.2012.2230587

    [8]

    Van d P G, Decoutere S, Donnay S. A 0.16 pJ/conversion-step 2.5 mW 1.25 GS/s 4 b ADC in a 90 nm digital CMOS process[J]. IEEE International Solid-State Circuits Conference (ISSCC), 2006: 2310.

    [9]

    Das I, Sahoo M, Roy P. A 45μW 13 pJ/conv-step 7.4-ENOB 40 kS/s SAR ADC for digital microfluidic biochip applications[J]. International Symposium on VlSI Design and Test, 2014: 1.

    [10]

    Shrivastava P, Bhat K G, Laxminidhi T. A 500 kS/s 8-bit charge recycle based 2-bit per step SAR-ADC[J]. Third International Conference on Emerging Applications of Information Technology, 2012: 462.

    [11]

    Nazzal T B, Mahmoud S A, Shaker M O. A 200-nW 7.6-ENOB 10-KS/s SAR ADC in 90-nm CMOS for Portable Biomedical Applications[J]. Microelectronics J, 2016, 56: 81. doi: 10.1016/j.mejo.2016.08.004

    [12]

    Mahmoud S A. An 8-bit, 10 kS/s, 1. 87μW successive approximation analog to digital converter in 0. 25μm CMOS technology for ECG detection systems. Circuits Systems & Signal Processing, 2015

    [13]

    Liu L Y, Li D M, Chen L D. A low power 8-bit successive approximation register A/D for a wireless body sensor node[J]. J Semicond, 2010, 31(6): 93.

    Search

    Advanced Search >>

    GET CITATION

    J H Duan, Z Y Zhu, J L Deng, W L Xu. An 8 bit 1 MS/s SAR ADC with 7.72-ENOB[J]. J. Semicond., 2017, 38(8): 085005. doi: 10.1088/1674-4926/38/8/085005.

    Export: BibTex EndNote

    Article Metrics

    Article views: 2295 Times PDF downloads: 39 Times Cited by: 0 Times

    History

    Manuscript received: 06 January 2017 Manuscript revised: 13 March 2017 Online: Published: 01 August 2017

    Email This Article

    User name:
    Email:*请输入正确邮箱
    Code:*验证码错误