J. Semicond. > Volume 38 > Issue 8 > Article Number: 085005

An 8 bit 1 MS/s SAR ADC with 7.72-ENOB

Jihai Duan , , Zhiyong Zhu , Jinli Deng and Weilin Xu

+ Author Affilications + Find other works by these authors

PDF

Abstract: This paper presents a low power 8-bit 1 MS/s SAR ADC with 7.72-bit ENOB. Without an op-amp, an improved segmented capacitor DAC is proposed to reduce the capacitance and the chip area. A dynamic latch comparator with output offset voltage storage technology is used to improve the precision. Adding an extra positive feedback in the latch is to increase the speed. What is more, two pairs of CMOS switches are utilized to eliminate the kickback noise introduced by the latch. The proposed SAR ADC was fabricated in SMIC 0.18 μm CMOS technology. The measured results show that this design achieves an SFDR of 61.8 dB and an ENOB of 7.72 bits, and it consumes 67.5 μ W with the FOM of 312 fJ/conversion-step at 1 MS/s sample under 1.8 V power supply.

Key words: SAR ADCdynamic latch comparatoroutput offset voltage storage technologykickback noise

Abstract: This paper presents a low power 8-bit 1 MS/s SAR ADC with 7.72-bit ENOB. Without an op-amp, an improved segmented capacitor DAC is proposed to reduce the capacitance and the chip area. A dynamic latch comparator with output offset voltage storage technology is used to improve the precision. Adding an extra positive feedback in the latch is to increase the speed. What is more, two pairs of CMOS switches are utilized to eliminate the kickback noise introduced by the latch. The proposed SAR ADC was fabricated in SMIC 0.18 μm CMOS technology. The measured results show that this design achieves an SFDR of 61.8 dB and an ENOB of 7.72 bits, and it consumes 67.5 μ W with the FOM of 312 fJ/conversion-step at 1 MS/s sample under 1.8 V power supply.

Key words: SAR ADCdynamic latch comparatoroutput offset voltage storage technologykickback noise



References:

[1]

Ginsburg B P, Chandrakasan A P. Highly interleaved 5-bit, 250-MSample/s, 1.2-mW ADC with redundant channels in 65-nm CMOS[J]. IEEE J Solid-State Circuits, 2008, 43(12): 2641. doi: 10.1109/JSSC.2008.2006334

[2]

Cao T V, Aunet S, Ytterdal T. A 9-bit 50MS/s asynchronous SAR ADC in 28 nm CMOS[J]. Norchip, 2012: 1.

[3]

Zhang H, Qin Y J, Yang S Y. A 455 nW 220 fJ/conversion-step 12 bits 2 kS/s SAR ADC for portable biopotential acquisition systems[J]. J Semicond, 2011, 32(1): 79.

[4]

Shen Y, Liu S, Zhu Z. A 12-bit 50MS/s zero-crossing-based two-stage pipelined SAR ADC in 0.18μm CMOS[J]. Microelectron J, 2016, 57: 26. doi: 10.1016/j.mejo.2016.09.002

[5]

Muratore D G, Bonizzoni E, Maloberti F. A split transconductor high-speed SAR ADC[J]. IEEE International Symposium on Circuits and Systems, 2015: 2433.

[6]

Liu W, Wei T, Guo P. Design of a novel 12-bit 1MS/s charge redistribution SAR ADC for CZT detectors[J]. IEEE Conference on Industrial Electronics and Applications, 2014: 867.

[7]

Hu W, Liu Y T, Nguyen T. An 8-bit single-ended ultra-low-power SAR ADC with a novel DAC switching method and a counter-based digital control circuitry[J]. IEEE Trans Circuits Syst I, 2013, 60(7): 1726. doi: 10.1109/TCSI.2012.2230587

[8]

Van d P G, Decoutere S, Donnay S. A 0.16 pJ/conversion-step 2.5 mW 1.25 GS/s 4 b ADC in a 90 nm digital CMOS process[J]. IEEE International Solid-State Circuits Conference (ISSCC), 2006: 2310.

[9]

Das I, Sahoo M, Roy P. A 45μW 13 pJ/conv-step 7.4-ENOB 40 kS/s SAR ADC for digital microfluidic biochip applications[J]. International Symposium on VlSI Design and Test, 2014: 1.

[10]

Shrivastava P, Bhat K G, Laxminidhi T. A 500 kS/s 8-bit charge recycle based 2-bit per step SAR-ADC[J]. Third International Conference on Emerging Applications of Information Technology, 2012: 462.

[11]

Nazzal T B, Mahmoud S A, Shaker M O. A 200-nW 7.6-ENOB 10-KS/s SAR ADC in 90-nm CMOS for Portable Biomedical Applications[J]. Microelectronics J, 2016, 56: 81. doi: 10.1016/j.mejo.2016.08.004

[12]

Mahmoud S A. An 8-bit, 10 kS/s, 1. 87μW successive approximation analog to digital converter in 0. 25μm CMOS technology for ECG detection systems. Circuits Systems & Signal Processing, 2015

[13]

Liu L Y, Li D M, Chen L D. A low power 8-bit successive approximation register A/D for a wireless body sensor node[J]. J Semicond, 2010, 31(6): 93.

[1]

Ginsburg B P, Chandrakasan A P. Highly interleaved 5-bit, 250-MSample/s, 1.2-mW ADC with redundant channels in 65-nm CMOS[J]. IEEE J Solid-State Circuits, 2008, 43(12): 2641. doi: 10.1109/JSSC.2008.2006334

[2]

Cao T V, Aunet S, Ytterdal T. A 9-bit 50MS/s asynchronous SAR ADC in 28 nm CMOS[J]. Norchip, 2012: 1.

[3]

Zhang H, Qin Y J, Yang S Y. A 455 nW 220 fJ/conversion-step 12 bits 2 kS/s SAR ADC for portable biopotential acquisition systems[J]. J Semicond, 2011, 32(1): 79.

[4]

Shen Y, Liu S, Zhu Z. A 12-bit 50MS/s zero-crossing-based two-stage pipelined SAR ADC in 0.18μm CMOS[J]. Microelectron J, 2016, 57: 26. doi: 10.1016/j.mejo.2016.09.002

[5]

Muratore D G, Bonizzoni E, Maloberti F. A split transconductor high-speed SAR ADC[J]. IEEE International Symposium on Circuits and Systems, 2015: 2433.

[6]

Liu W, Wei T, Guo P. Design of a novel 12-bit 1MS/s charge redistribution SAR ADC for CZT detectors[J]. IEEE Conference on Industrial Electronics and Applications, 2014: 867.

[7]

Hu W, Liu Y T, Nguyen T. An 8-bit single-ended ultra-low-power SAR ADC with a novel DAC switching method and a counter-based digital control circuitry[J]. IEEE Trans Circuits Syst I, 2013, 60(7): 1726. doi: 10.1109/TCSI.2012.2230587

[8]

Van d P G, Decoutere S, Donnay S. A 0.16 pJ/conversion-step 2.5 mW 1.25 GS/s 4 b ADC in a 90 nm digital CMOS process[J]. IEEE International Solid-State Circuits Conference (ISSCC), 2006: 2310.

[9]

Das I, Sahoo M, Roy P. A 45μW 13 pJ/conv-step 7.4-ENOB 40 kS/s SAR ADC for digital microfluidic biochip applications[J]. International Symposium on VlSI Design and Test, 2014: 1.

[10]

Shrivastava P, Bhat K G, Laxminidhi T. A 500 kS/s 8-bit charge recycle based 2-bit per step SAR-ADC[J]. Third International Conference on Emerging Applications of Information Technology, 2012: 462.

[11]

Nazzal T B, Mahmoud S A, Shaker M O. A 200-nW 7.6-ENOB 10-KS/s SAR ADC in 90-nm CMOS for Portable Biomedical Applications[J]. Microelectronics J, 2016, 56: 81. doi: 10.1016/j.mejo.2016.08.004

[12]

Mahmoud S A. An 8-bit, 10 kS/s, 1. 87μW successive approximation analog to digital converter in 0. 25μm CMOS technology for ECG detection systems. Circuits Systems & Signal Processing, 2015

[13]

Liu L Y, Li D M, Chen L D. A low power 8-bit successive approximation register A/D for a wireless body sensor node[J]. J Semicond, 2010, 31(6): 93.

[1]

Wei Liu, Tingcun Wei, Bo Li, Lifeng Yang, Yongcai Hu. A reference voltage in capacitor-resister hybrid SAR ADC for front-end readout system of CZT detector. J. Semicond., 2016, 37(1): 015005. doi: 10.1088/1674-4926/37/1/015005

[2]

Beichen Zhang, Bingbing Yao, Liyuan Liu, Jian Liu, Nanjian Wu. High power-efficient asynchronous SAR ADC for IoT devices. J. Semicond., 2017, 38(10): 105001. doi: 10.1088/1674-4926/38/10/105001

[3]

Jingjing Wang, Zemin Feng, Rongjin Xu, Chixiao Chen, Fan Ye, Jun Xu, Junyan Ren. A 100 MS/s 9 bit 0.43 mW SAR ADC with custom capacitor array. J. Semicond., 2016, 37(5): 055003. doi: 10.1088/1674-4926/37/5/055003

[4]

Dong Li, Qiao Meng, Fei Li. A 10 bit 50 MS/s SAR ADC with partial split capacitor switching scheme in 0.18 μm CMOS. J. Semicond., 2016, 37(1): 015004. doi: 10.1088/1674-4926/37/1/015004

[5]

Yuxiao Lu, Lu Sun, Zhe Li, Jianjun Zhou. A single-channel 10-bit 160 MS/s SAR ADC in 65 nm CMOS. J. Semicond., 2014, 35(4): 045009. doi: 10.1088/1674-4926/35/4/045009

[6]

Yan Song, Zhongming Xue, Pengcheng Yan, Jueying Zhang, Li Geng. A 0.6-V 8.3-ENOB asynchronous SAR ADC for biomedical applications. J. Semicond., 2014, 35(8): 085007. doi: 10.1088/1674-4926/35/8/085007

[7]

Hui Hong, Shiliang Li, Tao Zhou. Design of a low power 10 bit 300 ksps multi-channel SAR ADC for wireless sensor network applications. J. Semicond., 2015, 36(4): 045009. doi: 10.1088/1674-4926/36/4/045009

[8]

Mingyuan Yu, Ting Li, Jiaqi Yang, Shuangshuang Zhang, Fujiang Lin, Lin He. A 1 V 186-μW 50-MS/s 10-bit subrange SAR ADC in 130-nm CMOS process. J. Semicond., 2016, 37(7): 075005. doi: 10.1088/1674-4926/37/7/075005

[9]

Jixuan Xiang, Chixiao Chen, Fan Ye, Jun Xu, Ning Li, Junyan Ren. A 6-b 600 MS/s SAR ADC with a new switching procedure of 2-b/stage and self-locking comparators. J. Semicond., 2015, 36(5): 055009. doi: 10.1088/1674-4926/36/5/055009

[10]

Wei Lü, Duona Luo, Fengcheng Mei, Jiaqi Yang, Libin Yao, Lin He, Fujiang Lin. A 0.6 V 10 bit 1 MS/s monotonic switching SAR ADC with common mode stabilizer in 0.13 μm CMOS. J. Semicond., 2014, 35(5): 055006. doi: 10.1088/1674-4926/35/5/055006

[11]

Yun Gui, Xu Zhang, Yuan Wang, Ming Liu, Weihua Pei, Kai Liang, Suibiao Huang, Bin Li, Hongda Chen. A multi-channel fully differential programmable integrated circuit for neural recording application. J. Semicond., 2013, 34(10): 105009. doi: 10.1088/1674-4926/34/10/105009

[12]

Liangbo Xie, Jiaxin Liu, Yao Wang, Guangjun Wen. A low-power CMOS smart temperature sensor for RFID application. J. Semicond., 2014, 35(11): 115002. doi: 10.1088/1674-4926/35/11/115002

[13]

Xiaofei Pu, Lei Wan, Hui Zhang, Yajie Qin, Zhiliang Hong. A low-power portable ECG sensor interface with dry electrodes. J. Semicond., 2013, 34(5): 055002. doi: 10.1088/1674-4926/34/5/055002

[14]

Shubin Liu, Zhangming Zhu, Yintang Yang, Lianxi Liu. A high speed low power low offset dynamic comparator used in SHA-less pipelined ADC. J. Semicond., 2014, 35(5): 055008. doi: 10.1088/1674-4926/35/5/055008

[15]

Tong Xingyuan, Zhu Zhangming, Yang Yintang. An offset cancellation technique in a switched-capacitor comparator for SAR ADCs. J. Semicond., 2012, 33(1): 015011. doi: 10.1088/1674-4926/33/1/015011

[16]

Yang Siyu, Zhang Hui, Fu Wenhui, Yi Ting, Hong Zhiliang. A low power 12-bit 200-kS/s SAR ADC with a differential time domain comparator. J. Semicond., 2011, 32(3): 035002. doi: 10.1088/1674-4926/32/3/035002

[17]

Xue Han, Hua Fan, Qi Wei, Huazhong Yang. A high SFDR 6-bit 20-MS/s SAR ADC based on time-domain comparator. J. Semicond., 2013, 34(8): 085008. doi: 10.1088/1674-4926/34/8/085008

[18]

Fan Hua, Wei Qi, Kobenge Sekedi Bomeh, Yin Xiumei, Yang Huazhong. An 8-bit 180-kS/s differential SAR ADC with a time-domain comparator and 7.97-ENOB. J. Semicond., 2010, 31(9): 095011. doi: 10.1088/1674-4926/31/9/095011

[19]

Yang Jinda, Wang Xianbiao, Li Li, Cheng Xu, Guo Yawei, Zeng Xiaoyang. A novel low-offset dynamic comparator for sub-1-V pipeline ADCs. J. Semicond., 2011, 32(8): 085005. doi: 10.1088/1674-4926/32/8/085005

[20]

Quanliang Li, Liyuan Liu, Ye Han, Zhongxiang Cao, Nanjian Wu. A 12-bit compact column-parallel SAR ADC with dynamic power control technique for high-speed CMOS image sensors. J. Semicond., 2014, 35(10): 105008. doi: 10.1088/1674-4926/35/10/105008

Search

Advanced Search >>

GET CITATION

J H Duan, Z Y Zhu, J L Deng, W L Xu. An 8 bit 1 MS/s SAR ADC with 7.72-ENOB[J]. J. Semicond., 2017, 38(8): 085005. doi: 10.1088/1674-4926/38/8/085005.

Export: BibTex EndNote

Article Metrics

Article views: 533 Times PDF downloads: 18 Times Cited by: 0 Times

History

Manuscript received: 06 January 2017 Manuscript revised: 13 March 2017 Online: Published: 01 August 2017

Email This Article

User name:
Email:*请输入正确邮箱
Code:*验证码错误