J. Semicond. > Volume 38 > Issue 8 > Article Number: 085008

A 4 Gbps current-mode transmitter for 12-bit 250 MSPS ADC

Zhenhai Chen 1, 3, , Zongguang Yu 1, 2, , , Jinghe Wei 1, , Dejin Zhou 3, , Xiaobo Su 2, 1, and Jiaxuan Zou 2, 1,

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Abstract: A 4 Gbps transmitter for a 12-bit 250 MSPS pipelined ADCs is presented. A low power current mode (CM) output driver with reverse scaling technique is proposed. A high speed, low power combined serializer is implemented to convert 12 bit parallel data into a seria1 data stream. The whole transmitter is used in a 12-bit 250 MSPS pipelined ADC for the digital output buffer and fabricated in 180 nm 1. 8 V 1P5M CMOS technology. Test results show that the transmitter provides an eye height greater than 800 mV for data rates of both 2 Gbps and 4 Gbps, the 12-bit 250 MSPS ADC achieves the SNR of 69.92 dBFS and SFDR of 81.17 dB with 20.1 MHz input at full sampling speed. The ADC with the 4 Gbps transmitter consumes the power consumption of 395 mW, where the power consumption of transmitter is 75 mW. The ADC occupies an area of 2.5×3.2 mm2, where the active area of the transmitter block is 0.5×1.2 mm2.

Key words: interfacepipelined ADCtransmittercurrent mode

Abstract: A 4 Gbps transmitter for a 12-bit 250 MSPS pipelined ADCs is presented. A low power current mode (CM) output driver with reverse scaling technique is proposed. A high speed, low power combined serializer is implemented to convert 12 bit parallel data into a seria1 data stream. The whole transmitter is used in a 12-bit 250 MSPS pipelined ADC for the digital output buffer and fabricated in 180 nm 1. 8 V 1P5M CMOS technology. Test results show that the transmitter provides an eye height greater than 800 mV for data rates of both 2 Gbps and 4 Gbps, the 12-bit 250 MSPS ADC achieves the SNR of 69.92 dBFS and SFDR of 81.17 dB with 20.1 MHz input at full sampling speed. The ADC with the 4 Gbps transmitter consumes the power consumption of 395 mW, where the power consumption of transmitter is 75 mW. The ADC occupies an area of 2.5×3.2 mm2, where the active area of the transmitter block is 0.5×1.2 mm2.

Key words: interfacepipelined ADCtransmittercurrent mode



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Fukuda K, Yamashita H, Ono G. A 123 mW 125 Gbps complete transceiver in 65 nm CMOS process[J]. IEEE J Solid-State Circuits, 2010, 45(12): 2838. doi: 10.1109/JSSC.2010.2075410

[2]

Liu Y, Hsieh P H, Kim S. A 0.1 pJ/b 5-to-10Gb/s chargerecycling stacked low-power I/O for on-chip signaling in 45 nm CMOS SOI[J]. IEEE J Solid-State Circuits, 2013, 48(12): 2905.

[3]

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[4]

Han S, Lee S, Choi M. A coefficient-error-robust FFE TX with 230% eye-variation improvement without calibration in 65 nm CMOS technology[J]. Proc ISSCC, 2014: 50.

[5]

Kim B, Liu Y, Dickson O. A 10-Gb/s compact low-power serial I/O with DFE-ⅡR equalization in 65-nm CMOS[J]. IEEE J Solid-State Circuits, 2009, 44(12): 3526. doi: 10.1109/JSSC.2009.2031015

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Schrader J, Klumperrink E A M, Visschers J. Pulse width modulation preemphasis applied in a wireline transmitter, achieving 33 dB loss compensation at 5 Gbps in 0.13 m CMOS[J]. IEEE J Solid-State Circuits, 2009, 41(4): 990.

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Zhang M K, Hu Q S. A 6.25 Gb/s equalizer in 0.18 m CMOS technology for high-speed SerDes[J]. J Semicond, 2013, 34(12): 125010. doi: 10.1088/1674-4926/34/12/125010

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Ln J S, Ju H, Ye M. A 5 Gb/s low power current-mode transmitter with pre-emphasis for serial links[J]. J Semicond, 2013, 34(7): 075002. doi: 10.1088/1674-4926/34/7/075002

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[10]

Xuan W, Chang Y Y, Xiao X Z. A 12-bit, 270 MS/s pipelined ADC with SHA-eliminating front end[J]. IEEE Int Circ Syst, Seoul, Korea, 2012: 798.

[11]

Liechti T, Tajalli A, Akgun O C. A 1.8 V 12-bit 230-MS/s pipeline ADC in 0.18 m CMOS technology[J]. IEEE Int Circ Syst, Macao, China, 2008: 21.

[12]

Wang R, Chio U F, Sin S W. A 12-bit 110-MS/s 4-stage single-opamp pipelined SAR ADC with ratio-based GEC technique[J]. Proc ESSCIRC, Bordeaux, France, 2012: 265.

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Shin S K, Rudell J C, Daily D C. A 12-bit, 20 MS/s zerocrossing based pipelined ADC with early sub-ADC decision and output residue background calibration[J]. IEEE J Solid-State Circuits, 2014, 49(6): 1366. doi: 10.1109/JSSC.2014.2322853

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Z H Chen, Z G Yu, J H Wei, D J Zhou, X B Su, J X Zou. A 4 Gbps current-mode transmitter for 12-bit 250 MSPS ADC[J]. J. Semicond., 2017, 38(8): 085008. doi: 10.1088/1674-4926/38/8/085008.

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History

Manuscript received: 27 October 2016 Manuscript revised: 21 January 2017 Online: Published: 01 August 2017

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