J. Semicond. > Volume 39 > Issue 10 > Article Number: 104004

Two dimensional analytical model for a negative capacitance double gate tunnel field effect transistor with ferroelectric gate dielectric

Huifang Xu ,

+ Author Affilications + Find other works by these authors

PDF

Turn off MathJax

Abstract: Analytical models are presented for a negative capacitance double-gate tunnel field-effect transistor (NC DG TFET) with a ferroelectric gate dielectric in this paper. The model accurately calculates the channel potential profile by solving the Poisson equation with the Landau–Khalatnikov (LK) equation. Moreover, the effects of the channel mobile charges on the potential are also taken into account. We also analyze the dependences of the channel potential and the on-state current on the device parameters by changing the thickness of ferroelectric layer, ferroelectric material and also verify the simulation results accord with commercial TCAD. The results show that the device can obtain better characteristics when the thickness of the ferroelectric layer is larger as it can reduce the shortest tunneling length.

Key words: ferroelectric gate dielectricdouble-gate tunnel field-effect transistoranalytical model

Abstract: Analytical models are presented for a negative capacitance double-gate tunnel field-effect transistor (NC DG TFET) with a ferroelectric gate dielectric in this paper. The model accurately calculates the channel potential profile by solving the Poisson equation with the Landau–Khalatnikov (LK) equation. Moreover, the effects of the channel mobile charges on the potential are also taken into account. We also analyze the dependences of the channel potential and the on-state current on the device parameters by changing the thickness of ferroelectric layer, ferroelectric material and also verify the simulation results accord with commercial TCAD. The results show that the device can obtain better characteristics when the thickness of the ferroelectric layer is larger as it can reduce the shortest tunneling length.

Key words: ferroelectric gate dielectricdouble-gate tunnel field-effect transistoranalytical model



References:

[1]

Prabhat V, Dutta A K. Analytical surface potential and drain current models of dual-metal-gate double-gate tunnel-FETs. IEEE Trans Electron Devices, 2016, 63(5): 2190

[2]

Mohammadi S, Khaveh H R T. An analytical model for double-gate tunnel FETs considering the junctions depletion regions and the channel mobile charge carriers. IEEE Trans Electron Devices, 2017, 64(3): 1268

[3]

Nupur N, Abhinav K. Overcoming the drawback of lower sense margin in tunnel FET based dynamic memory along with enhanced charge retention and scalability. Nanotechnology, 2017, 28: 445203

[4]

Kumar S, Goel E, Singh K, et al. A compact 2-D analytical model for electrical characteristics of double-gate tunnel field-effect transistors with a SiO2/high-k stacked gate-oxide structure. IEEE Trans Electron Devices, 2016, 63(8): 3291

[5]

Navjeet B, Subir K S. An analytical model for tunnel barrier modulation in triple metal double gate TFET. IEEE Trans Electron Devices, 2015, 62(7): 2136

[6]

Hraziia, Vladimirescu A, Amara A, et al. An analysis on the ambipolar current in Si double-gate tunnel FETs. Solid-State Electron, 2012, 70(4): 67

[7]

Wu J Z, Taur Y. Reduction of TFET OFF-current and subthreshold swing by lightly doped drain. IEEE Trans Electron Devices, 2016, 63(8): 3342

[8]

Nigam K, Pandey S, Kondekar P N, et al. A barrier controlled charge plasma-based tfet with gate engineering for ambipolar suppression and RF/linearity performance improvement. IEEE Trans Electron Devices, 2017, 64(6): 2751

[9]

Raad B R, Sharma D, Kondekar P, et al. Drain work function engineered doping-less charge plasma TFET for ambipolar suppression and RF performance improvement: A proposal, design, and investigation. IEEE Trans Electron Devices, 2016, 63(10): 3950

[10]

Ko E, Lee H, Park J D, et al. Vertical tunnel FET: design optimization with triple metal-gate layers. IEEE Trans Electron Devices, 2016, 63(12): 5030

[11]

Boucart K, Ionescu A M. Double-gate tunnel FET with high-k gate dielectric. IEEE Trans Electron Devices, 2007, 54(7): 1725

[12]

Kao K H, Verhulst A S, Vandenberghe W G, et al. Direct and indirect band-to-band tunneling in germanium-based TFETs. IEEE Trans Electron Devices, 2012, 59(2): 292

[13]

Ahish S, Sharma D, Kumar Y B N, et al. Performance enhancement of novel InAs/Si hetero double-gate tunnel FET using gaussian doping. IEEE Trans Electron Devices, 2016, 63(1): 288

[14]

Yadav D S, Sharma D, Kumar A, et al. Performance investigation of hetero material (InAs/Si)-based charge plasma TFET. Micro Nano Lett, 2017, 12(6): 358

[15]

Bagga N, Dasgupta S. Surface potential and drain current analytical model of gate all around triple metal TFET. IEEE Trans Electron Devices, 2017, 64(2): 606

[16]

Abdi D B, Kumar M J. 2-D Threshold voltage model for the double-gate p–n–p–n TFET with localized charges. IEEE Trans Electron Devices, 2016, 63(9): 3663

[17]

Wang Y B, Han G Q, Liu Y, et al. Investigation of GaAsBi/GaAsN type-II staggered heterojunction TFETs with the analytical model. IEEE Trans Electron Devices, 2017, 64(4): 1541

[18]

Xu H F, Guan B G. Two-dimensional analytical model for hetero-junction double-gate tunnel field-effect transistor with a stacked gate-oxide structure. Jpn J Appl Phys, 2017, 56(5): 054201

[19]

Zhao Y, Wu C L, Huang Q Q, et al. A novel tunnel FET design through adaptive bandgap engineering with constant sub-threshold slope over 5 decades of current and high ION/IOFF ratio. IEEE Electron Device Lett, 2017, 38(5): 540

[20]

Kondekar P N, Nigam K, Pandey S, et al. Design and analysis of polarity controlled electrically doped tunnel FET with bandgap engineering for analog/RF applications. IEEE Trans Electron Devices, 2017, 64(2): 412

[21]

Lahgere A, Panchore M, Singh J. Dopingless ferroelectric tunnel FET architecture for the improvement of performance of dopingless n-channel tunnel FETs. Superlattices Microstruct, 2016, 96: 16

[22]

Kale S, Kondekar P N. Ferroelectric Schottky barrier tunnel FET with gate-drain underlap: Proposal and investigation. Superlattices Microstruct., 2016, 89: 225.

[23]

Lee M H, Wei Y T, Lin J C, et al. Ferroelectric gate tunnel field-effect transistors with low-power steep turn-on. AIP Adv, 2014, 4(10): 107117

[24]

Kobayashi M, Jang K, Ueyama N, et al. Negative capacitance for boosting tunnel FET performance. IEEE Trans Nanotechnol, 2017, 16(2): 253

[25]

Liu C, Chen P G, Xie M J, et al. Simulation-based study of negative-capacitance double-gate tunnel field-effect transistor with ferroelectric gate stack. Jpn J Appl Phys, 2016, 55(4S): 04EB08

[26]

Saeidi A, Biswas A, Ionescu A M. Modeling and simulation of low power ferroelectric non-volatile memory tunnel field effect transistors using silicon-doped hafnium oxide as gate dielectric. Solid-State Electron, 2016, 124(10): 16

[27]

Chowdhury N, Azad S M F, Khosru Q D M. Negative capacitance tunnel field effect transistor: A novel device with low subthreshold swing and high on current. ECS Trans, 2014, 58(16): 1

[28]

Chowdhury N, Ahmed I, Fakhrul T, et al. A low subthreshold swing tunneling field effect transistor for next generation low power CMOS applications. Physica E, 2015, 74(11): 251

[29]

Jiang C S, Liang R R, Xu J. Investigation of negative capacitance gate-all-around tunnel FETs combining numerical simulation and analytical modeling. IEEE Trans Nanotechnol, 2017, 16(1): 58

[30]

ATLAS User’s Manual (Silvaco Int., Santa Clara, CA, 2012).

[31]

Girish P, Tapas D, Amit A, et al. Compact model for ferroelectric negative capacitance transistor with MFIS structure. IEEE Trans Electron Devices, 2017, 64(3): 1366

[32]

Cheng I L, Asif I K, Sayeef S, et al. Effects of the variation of ferroelectric properties on negative capacitance FET characteristics. IEEE Trans Electron Devices, 2016, 63(5): 2197

[1]

Prabhat V, Dutta A K. Analytical surface potential and drain current models of dual-metal-gate double-gate tunnel-FETs. IEEE Trans Electron Devices, 2016, 63(5): 2190

[2]

Mohammadi S, Khaveh H R T. An analytical model for double-gate tunnel FETs considering the junctions depletion regions and the channel mobile charge carriers. IEEE Trans Electron Devices, 2017, 64(3): 1268

[3]

Nupur N, Abhinav K. Overcoming the drawback of lower sense margin in tunnel FET based dynamic memory along with enhanced charge retention and scalability. Nanotechnology, 2017, 28: 445203

[4]

Kumar S, Goel E, Singh K, et al. A compact 2-D analytical model for electrical characteristics of double-gate tunnel field-effect transistors with a SiO2/high-k stacked gate-oxide structure. IEEE Trans Electron Devices, 2016, 63(8): 3291

[5]

Navjeet B, Subir K S. An analytical model for tunnel barrier modulation in triple metal double gate TFET. IEEE Trans Electron Devices, 2015, 62(7): 2136

[6]

Hraziia, Vladimirescu A, Amara A, et al. An analysis on the ambipolar current in Si double-gate tunnel FETs. Solid-State Electron, 2012, 70(4): 67

[7]

Wu J Z, Taur Y. Reduction of TFET OFF-current and subthreshold swing by lightly doped drain. IEEE Trans Electron Devices, 2016, 63(8): 3342

[8]

Nigam K, Pandey S, Kondekar P N, et al. A barrier controlled charge plasma-based tfet with gate engineering for ambipolar suppression and RF/linearity performance improvement. IEEE Trans Electron Devices, 2017, 64(6): 2751

[9]

Raad B R, Sharma D, Kondekar P, et al. Drain work function engineered doping-less charge plasma TFET for ambipolar suppression and RF performance improvement: A proposal, design, and investigation. IEEE Trans Electron Devices, 2016, 63(10): 3950

[10]

Ko E, Lee H, Park J D, et al. Vertical tunnel FET: design optimization with triple metal-gate layers. IEEE Trans Electron Devices, 2016, 63(12): 5030

[11]

Boucart K, Ionescu A M. Double-gate tunnel FET with high-k gate dielectric. IEEE Trans Electron Devices, 2007, 54(7): 1725

[12]

Kao K H, Verhulst A S, Vandenberghe W G, et al. Direct and indirect band-to-band tunneling in germanium-based TFETs. IEEE Trans Electron Devices, 2012, 59(2): 292

[13]

Ahish S, Sharma D, Kumar Y B N, et al. Performance enhancement of novel InAs/Si hetero double-gate tunnel FET using gaussian doping. IEEE Trans Electron Devices, 2016, 63(1): 288

[14]

Yadav D S, Sharma D, Kumar A, et al. Performance investigation of hetero material (InAs/Si)-based charge plasma TFET. Micro Nano Lett, 2017, 12(6): 358

[15]

Bagga N, Dasgupta S. Surface potential and drain current analytical model of gate all around triple metal TFET. IEEE Trans Electron Devices, 2017, 64(2): 606

[16]

Abdi D B, Kumar M J. 2-D Threshold voltage model for the double-gate p–n–p–n TFET with localized charges. IEEE Trans Electron Devices, 2016, 63(9): 3663

[17]

Wang Y B, Han G Q, Liu Y, et al. Investigation of GaAsBi/GaAsN type-II staggered heterojunction TFETs with the analytical model. IEEE Trans Electron Devices, 2017, 64(4): 1541

[18]

Xu H F, Guan B G. Two-dimensional analytical model for hetero-junction double-gate tunnel field-effect transistor with a stacked gate-oxide structure. Jpn J Appl Phys, 2017, 56(5): 054201

[19]

Zhao Y, Wu C L, Huang Q Q, et al. A novel tunnel FET design through adaptive bandgap engineering with constant sub-threshold slope over 5 decades of current and high ION/IOFF ratio. IEEE Electron Device Lett, 2017, 38(5): 540

[20]

Kondekar P N, Nigam K, Pandey S, et al. Design and analysis of polarity controlled electrically doped tunnel FET with bandgap engineering for analog/RF applications. IEEE Trans Electron Devices, 2017, 64(2): 412

[21]

Lahgere A, Panchore M, Singh J. Dopingless ferroelectric tunnel FET architecture for the improvement of performance of dopingless n-channel tunnel FETs. Superlattices Microstruct, 2016, 96: 16

[22]

Kale S, Kondekar P N. Ferroelectric Schottky barrier tunnel FET with gate-drain underlap: Proposal and investigation. Superlattices Microstruct., 2016, 89: 225.

[23]

Lee M H, Wei Y T, Lin J C, et al. Ferroelectric gate tunnel field-effect transistors with low-power steep turn-on. AIP Adv, 2014, 4(10): 107117

[24]

Kobayashi M, Jang K, Ueyama N, et al. Negative capacitance for boosting tunnel FET performance. IEEE Trans Nanotechnol, 2017, 16(2): 253

[25]

Liu C, Chen P G, Xie M J, et al. Simulation-based study of negative-capacitance double-gate tunnel field-effect transistor with ferroelectric gate stack. Jpn J Appl Phys, 2016, 55(4S): 04EB08

[26]

Saeidi A, Biswas A, Ionescu A M. Modeling and simulation of low power ferroelectric non-volatile memory tunnel field effect transistors using silicon-doped hafnium oxide as gate dielectric. Solid-State Electron, 2016, 124(10): 16

[27]

Chowdhury N, Azad S M F, Khosru Q D M. Negative capacitance tunnel field effect transistor: A novel device with low subthreshold swing and high on current. ECS Trans, 2014, 58(16): 1

[28]

Chowdhury N, Ahmed I, Fakhrul T, et al. A low subthreshold swing tunneling field effect transistor for next generation low power CMOS applications. Physica E, 2015, 74(11): 251

[29]

Jiang C S, Liang R R, Xu J. Investigation of negative capacitance gate-all-around tunnel FETs combining numerical simulation and analytical modeling. IEEE Trans Nanotechnol, 2017, 16(1): 58

[30]

ATLAS User’s Manual (Silvaco Int., Santa Clara, CA, 2012).

[31]

Girish P, Tapas D, Amit A, et al. Compact model for ferroelectric negative capacitance transistor with MFIS structure. IEEE Trans Electron Devices, 2017, 64(3): 1366

[32]

Cheng I L, Asif I K, Sayeef S, et al. Effects of the variation of ferroelectric properties on negative capacitance FET characteristics. IEEE Trans Electron Devices, 2016, 63(5): 2197

[1]

Huifang Xu, Yuehua Dai. Two-dimensional analytical model of double-gate tunnel FETs with interface trapped charges including effects of channel mobile charge carriers. J. Semicond., 2017, 38(2): 024004. doi: 10.1088/1674-4926/38/2/024004

[2]

Changyong Zheng, Wei Zhang, Tailong Xu, Yuehua Dai, Junning Chen. A compact model for single material double work function gate MOSFET. J. Semicond., 2013, 34(9): 094006. doi: 10.1088/1674-4926/34/9/094006

[3]

T. Bendib, F. Djeffal, D. Arar. A compact charge-based model to study the nanoscale undoped double gate MOSFETs for nanoelectronic circuit design using genetic algorithms. J. Semicond., 2013, 34(4): 044003. doi: 10.1088/1674-4926/34/4/044003

[4]

Haimeng Huang, Xingbi Chen. An analytical model of the electric field distributions of buried superjunction devices. J. Semicond., 2013, 34(6): 064006. doi: 10.1088/1674-4926/34/6/064006

[5]

Li Zunchao, Jiang Yaolin, Wu Jianmin. Dual Material Gate SOI MOSFET with a Single Halo. J. Semicond., 2007, 28(3): 327.

[6]

Huifang Xu, Yuehua Dai, Ning Li, Jianbin Xu. A 2-D semi-analytical model of double-gate tunnel field-effect transistor. J. Semicond., 2015, 36(5): 054002. doi: 10.1088/1674-4926/36/5/054002

[7]

Li Xiaojian, Tan Yaohua, Tian Lilin. An Analytical Model of Electron Mobility for Strained-Si Channel nMOSFETs. J. Semicond., 2008, 29(5): 863.

[8]

Hengliang Zhao, Huilong Zhu, Jian Zhong, Xiaolong Ma, Xing Wei, Chao Zhao, Dapeng Chen, Tianchun Ye. Simulations of backgate sandwich nanowire MOSFETs with improved device performance. J. Semicond., 2014, 35(10): 104005. doi: 10.1088/1674-4926/35/10/104005

[9]

Han Lei, Huang Qing’an, Liao Xiaoping. Optimization of a Thermoelectric Microwave Power Sensor. J. Semicond., 2008, 29(4): 789.

[10]

Chen Cao, Bing Zhang, Longsheng Wu, Xin Li, Junfeng Wang. Pinch-off voltage modeling for CMOS image pixels with a pinned photodiode structure. J. Semicond., 2014, 35(7): 074012. doi: 10.1088/1674-4926/35/7/074012

[11]

Shoubhik Gupta, Bahniman Ghosh, Shiromani Balmukund Rahi. Compact analytical model of double gate junction-less field effect transistor comprising quantum-mechanical effect. J. Semicond., 2015, 36(2): 024001. doi: 10.1088/1674-4926/36/2/024001

[12]

Ding Qian, Wang Yu, Luo Rong, Wang Hui, Yang Huazhong. Soft error generation analysis in combinational logic circuits. J. Semicond., 2010, 31(9): 095015. doi: 10.1088/1674-4926/31/9/095015

[13]

M. W. Akram, Bahniman Ghosh, Punyasloka Bal, Partha Mondal. P-type double gate junctionless tunnel field effect transistor. J. Semicond., 2014, 35(1): 014002. doi: 10.1088/1674-4926/35/1/014002

[14]

M. W. Akram, Bahniman Ghosh. Analog performance of double gate junctionless tunnel field effect transistor. J. Semicond., 2014, 35(7): 074001. doi: 10.1088/1674-4926/35/7/074001

[15]

Meile Wu, Xiaoshi Jin, Rongyan Chuai, Xi Liu, Jong-Ho Lee. Simulation study on short channel double-gate junctionless field-effect transistors. J. Semicond., 2013, 34(3): 034004. doi: 10.1088/1674-4926/34/3/034004

[16]

Li Jin, Liu Hongxia, Yuan Bo, Cao Lei, Li Bin. A two-dimensional analytical model of fully depleted asymmetrical dual material gate double-gate strained-Si MOSFETs. J. Semicond., 2011, 32(4): 044005. doi: 10.1088/1674-4926/32/4/044005

[17]

Cui Ning, Liang Renrong, Wang Jing, Zhou Wei, Xu Jun. A PNPN tunnel field-effect transistor with high-k gate and low-k fringe dielectrics. J. Semicond., 2012, 33(8): 084004. doi: 10.1088/1674-4926/33/8/084004

[18]

Luan Suzhen, Liu Hongxia, Jia Renxu, Cai Naiqiong, Wang Jin, Kuang Qianwei. An Analytical Model of Drain Current for Ultra-Thin Body and Double-Gate Schottky Source/Drain MOSFETs Accounting for Quantum Effects. J. Semicond., 2008, 29(5): 869.

[19]

C. Usha, Dr. P. Vimala. A compact two-dimensional analytical model of the electrical characteristics of a triple-material double-gate tunneling FET structure. J. Semicond., 2019, 40(9): -1.

[20]

S. Intekhab Amin, R. K. Sarin. Direct tunneling gate current model for symmetric double gate junctionless transistor with SiO2/high-k gate stacked dielectric. J. Semicond., 2016, 37(3): 034001. doi: 10.1088/1674-4926/37/3/034001

Search

Advanced Search >>

GET CITATION

H F Xu, Two dimensional analytical model for a negative capacitance double gate tunnel field effect transistor with ferroelectric gate dielectric[J]. J. Semicond., 2018, 39(10): 104004. doi: 10.1088/1674-4926/39/10/104004.

Export: BibTex EndNote

Article Metrics

Article views: 1311 Times PDF downloads: 95 Times Cited by: 0 Times

History

Manuscript received: 01 January 2018 Manuscript revised: Online: Uncorrected proof: 05 July 2018 Published: 09 October 2018

Email This Article

User name:
Email:*请输入正确邮箱
Code:*验证码错误