J. Semicond. > Volume 39 > Issue 4 > Article Number: 044001

Design and simulation of nanoscale double-gate TFET/tunnel CNTFET

Shashi Bala , and Mamta Khosla

+ Author Affilications + Find other works by these authors

PDF

Turn off MathJax

Abstract: A double-gate tunnel field-effect transistor (DG tunnel FET) has been designed and investigated for various channel materials such as silicon (Si), gallium arsenide (GaAs), alminium gallium arsenide (AlxGa1−xAs) and CNT using a nano ViDES Device and TCAD SILVACO ATLAS simulator. The proposed devices are compared on the basis of inverse subthreshold slope (SS), ION/IOFF current ratio and leakage current. Using Si as the channel material limits the property to reduce leakage current with scaling of channel, whereas the AlxGa1−xAs based DG tunnel FET provides a better ION/IOFF current ratio (2.51 × 106) as compared to other devices keeping the leakage current within permissible limits. The performed silmulation of the CNT based channel in the double-gate tunnel field-effect transistor using the nano ViDES shows better performace for a sub-threshold slope of 29.4 mV/dec as the channel is scaled down. The proposed work shows the potential of the CNT channel based DG tunnel FET as a futuristic device for better switching and high retention time, which makes it suitable for memory based circuits.

Key words: band-to-band tunneling (BTBT)double gate (DG)silicon (Si)gallium arsenide (GaAs)aluminum gallium arsenide (AlxGa1−xAs)tunnel field effect transistor (FET)carbon nanotube (CNT)

Abstract: A double-gate tunnel field-effect transistor (DG tunnel FET) has been designed and investigated for various channel materials such as silicon (Si), gallium arsenide (GaAs), alminium gallium arsenide (AlxGa1−xAs) and CNT using a nano ViDES Device and TCAD SILVACO ATLAS simulator. The proposed devices are compared on the basis of inverse subthreshold slope (SS), ION/IOFF current ratio and leakage current. Using Si as the channel material limits the property to reduce leakage current with scaling of channel, whereas the AlxGa1−xAs based DG tunnel FET provides a better ION/IOFF current ratio (2.51 × 106) as compared to other devices keeping the leakage current within permissible limits. The performed silmulation of the CNT based channel in the double-gate tunnel field-effect transistor using the nano ViDES shows better performace for a sub-threshold slope of 29.4 mV/dec as the channel is scaled down. The proposed work shows the potential of the CNT channel based DG tunnel FET as a futuristic device for better switching and high retention time, which makes it suitable for memory based circuits.

Key words: band-to-band tunneling (BTBT)double gate (DG)silicon (Si)gallium arsenide (GaAs)aluminum gallium arsenide (AlxGa1−xAs)tunnel field effect transistor (FET)carbon nanotube (CNT)



References:

[1]

Sakurai T. Perspectives of low-power VLSI's. IEICE trans Electron, 2004, 87(4): 429

[2]

Bernstein K, Cavin R K, Porod W, et al. Device and architecture outlook for beyond CMOS switches. Proc IEEE, 2010, 98(12): 2169

[3]

Seabaugh A C, Zhang Q. Low-voltage tunnel transistors for beyond CMOS logic. Proc IEEE, 2010, 98(12): 2095

[4]

Zener C. A theory of the electrical breakdown of solid dielectrics. Proc Royal Soc London A, 1934, 145(855): 523

[5]

Silvaco ATLAS device simulator and user manual, silvaco int; Santa Clara, CA, USA 5.19.2 2013

[6]

Appenzeller J, Lin Y M, Knoch J, et al. Comparing carbon nanotube transistors-the ideal choice: a novel tunneling device design. IEEE Trans Electron Devices, 2005, 52(12): 2568

[7]

Sharma S K, Raj B, Khosla M. Comparative analysis of MOSFET, CNTFET and NWFET for energy efficient VLSI circuit design. J VLSI Des Tools Technol, 2016, 6: 1

[8]

Boucart K, Ionescu A M. Length scaling of the double gate tunnel FET with a high-k gate dielectric. Solid-State Electron, 2007, 51(11): 1500

[9]

Sharma S K, Raj B, Khosla M. A Gaussian approach for analytical subthreshold current model of cylindrical nanowire FET with quantum mechanical effects. Microelectron J, 2016, 53: 65

[10]

Sharma S K, Raj B, Khosla M. Subthreshold performance of In1−xGaxAs based dual metal with gate stack cylindrical/surrounding gate nanowire MOSFET for low power analog applications. J Nanoelectron Optoelectron, 2017, 12(2): 171

[11]

Zhang L, Lin X, He J, et al. An analytical charge model for double-gate tunnel FETs. IEEE Trans Electron Devices, 2012, 59(12): 3217

[12]

Kumar S, Raj B. Compact channel potential analytical modeling of DG-TFET based on Evanescent-mode approach. J Comput Electron, 2015, 14(3): 820

[13]

Singh A, Khosla M, Raj B. Analysis of electrostatic doped Schottky barrier carbon nanotube FET for low power applications. J Mater Sci: Mater Electron, 2017, 28(2): 1762

[14]

Singh K, Raj B. Temperature-dependent modeling and performance evaluation of multi-walled CNT and single-walled CNT as global interconnects. J Electron Mater, 2015, 44(12): 4825

[15]

Narang R, Saxena M, Gupta M, et al. Modeling and simulation of multi layer gate dielectric double gate tunnel field-effect transistor (DG-TFET). Students' Technology Symposium (TechSym), 2011: 281

[16]

Kumar S, Raj B. Analysis of ION and ambipolar current for dual-material gate–drain overlapped DG-TFET. J Nanoelectron Optoelectron, 2016, 11(3): 323

[17]

Singh K, Raj B. Performance and analysis of temperature dependent multi-walled carbon nanotubes as global interconnects at different technology nodes. J Comput Electron, 2015, 14(2): 469

[18]

Krishnamohan T, Kim D, Raghunathan S, et al. Double-gate strained-Ge heterostructure tunneling FET (TFET) with record high drive currents and $ \ll $ 60 mV/dec subthreshold slope. IEEE International Electron Devices Meeting, 2008: 1

[19]

Arun S, Balamurugan N B. An analytical modeling and simulation of dual material double gate tunnel field effect transistor for low power applications. J Electr Eng Technol, 2014, 9(1): 247

[20]

Singh A, Khosla M, Raj B. Compact model for ballistic single wall CNTFET under quantum capacitance limit. J Semicond, 2016, 37(10): 104001

[21]

Sahoo R, Mishra R R. Simulations of carbon nanotube field effect transistors. Int J Electron Eng Res, 2009, 1(2): 117

[22]

Singh A, Khosla M, Raj B. Compact model for ballistic single wall CNTFET under quantum capacitance limit. J Semicond, 2016, 37(10): 104001

[23]

Singh A, Khosla M, Raj B. Comparative analysis of carbon nanotube field effect transistor and nanowire transistor for low power circuit design. J Nanoelectron Optoelectron, 2016, 11(3): 388

[1]

Sakurai T. Perspectives of low-power VLSI's. IEICE trans Electron, 2004, 87(4): 429

[2]

Bernstein K, Cavin R K, Porod W, et al. Device and architecture outlook for beyond CMOS switches. Proc IEEE, 2010, 98(12): 2169

[3]

Seabaugh A C, Zhang Q. Low-voltage tunnel transistors for beyond CMOS logic. Proc IEEE, 2010, 98(12): 2095

[4]

Zener C. A theory of the electrical breakdown of solid dielectrics. Proc Royal Soc London A, 1934, 145(855): 523

[5]

Silvaco ATLAS device simulator and user manual, silvaco int; Santa Clara, CA, USA 5.19.2 2013

[6]

Appenzeller J, Lin Y M, Knoch J, et al. Comparing carbon nanotube transistors-the ideal choice: a novel tunneling device design. IEEE Trans Electron Devices, 2005, 52(12): 2568

[7]

Sharma S K, Raj B, Khosla M. Comparative analysis of MOSFET, CNTFET and NWFET for energy efficient VLSI circuit design. J VLSI Des Tools Technol, 2016, 6: 1

[8]

Boucart K, Ionescu A M. Length scaling of the double gate tunnel FET with a high-k gate dielectric. Solid-State Electron, 2007, 51(11): 1500

[9]

Sharma S K, Raj B, Khosla M. A Gaussian approach for analytical subthreshold current model of cylindrical nanowire FET with quantum mechanical effects. Microelectron J, 2016, 53: 65

[10]

Sharma S K, Raj B, Khosla M. Subthreshold performance of In1−xGaxAs based dual metal with gate stack cylindrical/surrounding gate nanowire MOSFET for low power analog applications. J Nanoelectron Optoelectron, 2017, 12(2): 171

[11]

Zhang L, Lin X, He J, et al. An analytical charge model for double-gate tunnel FETs. IEEE Trans Electron Devices, 2012, 59(12): 3217

[12]

Kumar S, Raj B. Compact channel potential analytical modeling of DG-TFET based on Evanescent-mode approach. J Comput Electron, 2015, 14(3): 820

[13]

Singh A, Khosla M, Raj B. Analysis of electrostatic doped Schottky barrier carbon nanotube FET for low power applications. J Mater Sci: Mater Electron, 2017, 28(2): 1762

[14]

Singh K, Raj B. Temperature-dependent modeling and performance evaluation of multi-walled CNT and single-walled CNT as global interconnects. J Electron Mater, 2015, 44(12): 4825

[15]

Narang R, Saxena M, Gupta M, et al. Modeling and simulation of multi layer gate dielectric double gate tunnel field-effect transistor (DG-TFET). Students' Technology Symposium (TechSym), 2011: 281

[16]

Kumar S, Raj B. Analysis of ION and ambipolar current for dual-material gate–drain overlapped DG-TFET. J Nanoelectron Optoelectron, 2016, 11(3): 323

[17]

Singh K, Raj B. Performance and analysis of temperature dependent multi-walled carbon nanotubes as global interconnects at different technology nodes. J Comput Electron, 2015, 14(2): 469

[18]

Krishnamohan T, Kim D, Raghunathan S, et al. Double-gate strained-Ge heterostructure tunneling FET (TFET) with record high drive currents and $ \ll $ 60 mV/dec subthreshold slope. IEEE International Electron Devices Meeting, 2008: 1

[19]

Arun S, Balamurugan N B. An analytical modeling and simulation of dual material double gate tunnel field effect transistor for low power applications. J Electr Eng Technol, 2014, 9(1): 247

[20]

Singh A, Khosla M, Raj B. Compact model for ballistic single wall CNTFET under quantum capacitance limit. J Semicond, 2016, 37(10): 104001

[21]

Sahoo R, Mishra R R. Simulations of carbon nanotube field effect transistors. Int J Electron Eng Res, 2009, 1(2): 117

[22]

Singh A, Khosla M, Raj B. Compact model for ballistic single wall CNTFET under quantum capacitance limit. J Semicond, 2016, 37(10): 104001

[23]

Singh A, Khosla M, Raj B. Comparative analysis of carbon nanotube field effect transistor and nanowire transistor for low power circuit design. J Nanoelectron Optoelectron, 2016, 11(3): 388

[1]

Pranav Kumar Asthana, Yogesh Goswami, Bahniman Ghosh. A novel sub 20 nm single gate tunnel field effect transistor with intrinsic channel forultra low power applications. J. Semicond., 2016, 37(5): 054002. doi: 10.1088/1674-4926/37/5/054002

[2]

Shiromani Balmukund Rahi, Bahniman Ghosh, Pranav Asthana. A simulation-based proposed high-k heterostructure AlGaAs/Si junctionless n-type tunnel FET. J. Semicond., 2014, 35(11): 114005. doi: 10.1088/1674-4926/35/11/114005

[3]

Libo Qian, Zhangming Zhu, Ruixue Ding, Yintang Yang. Circuit modeling and performance analysis of SWCNT bundle 3D interconnects. J. Semicond., 2013, 34(9): 095014. doi: 10.1088/1674-4926/34/9/095014

[4]

Bahniman Ghosh, Partha Mondal, M. W. Akram, Punyasloka Bal, Akshay Kumar Salimath. Hetero-gate-dielectric double gate junctionless transistor (HGJLT) with reduced band-to-band tunnelling effects in subthreshold regime. J. Semicond., 2014, 35(6): 064001. doi: 10.1088/1674-4926/35/6/064001

[5]

Wenqi Zhang, Zhiping Wang, Shiliang Ban. Optical absorption via intersubband transition of electrons in GaAs/AlxGa1−xAs multi-quantum wells in an electric field. J. Semicond., 2018, 39(12): 122002. doi: 10.1088/1674-4926/39/12/122002

[6]

Yipeng Jiao, Kangliang Wei, Taihuan Wang, Gang Du, Xiaoyan Liu. Comparison of band-to-band tunneling models in Si and Si-Ge junctions. J. Semicond., 2013, 34(9): 092002. doi: 10.1088/1674-4926/34/9/092002

[7]

M. W. Akram, Bahniman Ghosh, Punyasloka Bal, Partha Mondal. P-type double gate junctionless tunnel field effect transistor. J. Semicond., 2014, 35(1): 014002. doi: 10.1088/1674-4926/35/1/014002

[8]

M. W. Akram, Bahniman Ghosh. Analog performance of double gate junctionless tunnel field effect transistor. J. Semicond., 2014, 35(7): 074001. doi: 10.1088/1674-4926/35/7/074001

[9]

Zhu Huiwen, Liu Yongsong, Mao Lingfeng, Shen Jingqin, Zhu Zhiyan, Tang Weihua. Theoretical study of the SiO2/Si interface and its effect on energy band profile and MOSFET gate tunneling current. J. Semicond., 2010, 31(8): 082003. doi: 10.1088/1674-4926/31/8/082003

[10]

Huifang Xu. Two dimensional analytical model for a negative capacitance double gate tunnel field effect transistor with ferroelectric gate dielectric. J. Semicond., 2018, 39(10): 104004. doi: 10.1088/1674-4926/39/10/104004

[11]

Amandeep Singh, Dinesh Kumar Saini, Dinesh Agarwal, Sajal Aggarwal, Mamta Khosla, Balwinder Raj. Modeling and simulation of carbon nanotube field effect transistor and its circuit application. J. Semicond., 2016, 37(7): 074001. doi: 10.1088/1674-4926/37/7/074001

[12]

Huifang Xu, Yuehua Dai, Ning Li, Jianbin Xu. A 2-D semi-analytical model of double-gate tunnel field-effect transistor. J. Semicond., 2015, 36(5): 054002. doi: 10.1088/1674-4926/36/5/054002

[13]

Chen Shaofeng, Xia Shanhong, Song Qinglin, Hu Ping' an, Liu Yunqi, Zhu Daoben. Properties of Carbon Nanotube Field Emission. J. Semicond., 2003, 24(S1): 166.

[14]

Yogesh Goswami, Pranav Asthana, Bahniman Ghosh. Nanoscale Ⅲ-Ⅴ on Si-based junctionless tunnel transistor for EHF band applications. J. Semicond., 2017, 38(5): 054002. doi: 10.1088/1674-4926/38/5/054002

[15]

Zhu Ronghui, Zeng Yiping, Bu Junpeng, Hui Feng, Zheng Hongjun, Zhao Ji, Gao Yongliang. Correlation Between Arsenide Precipitation and Dislocations in Undoped LEC GaAs Crystal. J. Semicond., 2008, 29(9): 1779.

[16]

Bai Xianping, Ban Shiliang. Pressure Effect on Electronic Mobility in Quasi-Two-Dimensional AlxGa1-xAs/GaAs Heterojunction Systems. J. Semicond., 2005, 26(12): 2422.

[17]

Shibir Basak, Pranav Kumar Asthana, Yogesh Goswami, Bahniman Ghosh. Dynamic threshold voltage operation in Si and SiGe source junctionless tunnel field effect transistor. J. Semicond., 2014, 35(11): 114001. doi: 10.1088/1674-4926/35/11/114001

[18]

Cui Ning, Liang Renrong, Wang Jing, Zhou Wei, Xu Jun. A PNPN tunnel field-effect transistor with high-k gate and low-k fringe dielectrics. J. Semicond., 2012, 33(8): 084004. doi: 10.1088/1674-4926/33/8/084004

[19]

Yan Liu, Jing Yan, Hongjuan Wang, Genquan Han. Temperature dependent IDS-VGS characteristics of an N-channel Si tunneling field-effect transistor with a germanium source on Si(110) substrate. J. Semicond., 2014, 35(2): 024001. doi: 10.1088/1674-4926/35/2/024001

[20]

Shoubhik Gupta, Bahniman Ghosh, Shiromani Balmukund Rahi. Compact analytical model of double gate junction-less field effect transistor comprising quantum-mechanical effect. J. Semicond., 2015, 36(2): 024001. doi: 10.1088/1674-4926/36/2/024001

Search

Advanced Search >>

GET CITATION

S S B la, M Khosla. Design and simulation of nanoscale double-gate TFET/tunnel CNTFET[J]. J. Semicond., 2018, 39(4): 044001. doi: 10.1088/1674-4926/39/4/044001.

Export: BibTex EndNote

Article Metrics

Article views: 1627 Times PDF downloads: 117 Times Cited by: 0 Times

History

Manuscript received: 21 July 2017 Manuscript revised: 09 August 2017 Online: Uncorrected proof: 25 January 2018 Accepted Manuscript: 02 March 2018 Published: 01 April 2018

Email This Article

User name:
Email:*请输入正确邮箱
Code:*验证码错误