Fig. 1.
(Color online) DECODER circuit using NAND gate without SLEEP transistor.
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| Citation: |
Neha Gupta, Priyanka Parihar, Vaibhav Neema. Application of source biasing technique for energy efficient DECODER circuit design: memory array application[J]. Journal of Semiconductors, 2018, 39(4): 045001. doi: 10.1088/1674-4926/39/4/045001
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N Gupta, P Parihar, V Neema. Application of source biasing technique for energy efficient DECODER circuit design: memory array application[J]. J. Semicond., 2018, 39(4): 045001. doi: 10.1088/1674-4926/39/4/045001.
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Application of source biasing technique for energy efficient DECODER circuit design: memory array application
DOI: 10.1088/1674-4926/39/4/045001
More Information
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Abstract
Researchers have proposed many circuit techniques to reduce leakage power dissipation in memory cells. If we want to reduce the overall power in the memory system, we have to work on the input circuitry of memory architecture i.e. row and column decoder. In this research work, low leakage power with a high speed row and column decoder for memory array application is designed and four new techniques are proposed. In this work, the comparison of cluster DECODER, body bias DECODER, source bias DECODER, and source coupling DECODER are designed and analyzed for memory array application. Simulation is performed for the comparative analysis of different DECODER design parameters at 180 nm GPDK technology file using the CADENCE tool. Simulation results show that the proposed source bias DECODER circuit technique decreases the leakage current by 99.92% and static energy by 99.92% at a supply voltage of 1.2 V. The proposed circuit also improves dynamic power dissipation by 5.69%, dynamic PDP/EDP 65.03% and delay 57.25% at 1.2 V supply voltage.-
Keywords:
- SRAM,
- leakage current,
- delay,
- SLEEP transistor
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References
[1] Jiao H L, Qiu Y M, Kursun V. Low power and robust memory circuits with asymmetrical ground gating. Microelectron J, 2016, 48: 109 doi: 10.1016/j.mejo.2015.11.009[2] Turi M A, Delgado-Frias J G. High-performance low-power selective precharge schemes for address decoders. IEEE Trans Circuits Syst, 2008, 55(9): 917 doi: 10.1109/TCSII.2008.923435[3] Amrutur B S, Horowitz M A. Fast low-power decoders for RAMs. IEEE J Solid-State Circuits, 2001, 36(10): 1506 doi: 10.1109/4.953479[4] De V, Borkar S. Technology and design challenges for low power and high performance. Proc Int Symp Low Power Electron Des, 1999[5] Jain S, Chatterjee A K. NAND gate architectures for memory decoder. Int J Computs Technol, 2013: 610[6] Park J, Mooney V J, Pfeiffenberger P. Sleepy stack reduction in leakage power. Proc Int Workshop Power Timing Modeling, Optimize Simulation, 2004: 148[7] Turi M A, Delgado-Frias J G. High-performance low-power and sense-amp address decoders with selective precharging. IEEE Int Sympos Circuits, Devices, Syst, 2008, 55: 1464[8] Jiao H, Kursun V. Asymmetrical ground gating for low leakage and data robust sleep mode in memory banks. Proceedings of the IEEE Int Sympos VLSI Des, Autom Test, 2011: 205[9] Jia H L, Kursun V. Ground-bouncing-noise-aware combinational MTCMOS circuits. IEEE Trans Circuits Syst I, 2010, 57: 8[10] Neema V, Chouhan S, Tokekar S. Novel circuit technique for reduction of leakage current in series/parallel PMOS/NMOS transistors stack. IETE J Res, 2010, 56(6): 350[11] Sharma S, Kumar A, Pattanaik M, et al. Forward body biased multimode multi-threshold CMOS technique for ground bounce noise reduction in static CMOS adders. Int J Inform Electron Eng, 2013, 3: 6[12] Kursun V, Friedman E G. Multi-voltage CMOS circuit design. John Wiley & Sons Ltd, 2006: 58[13] Gupta N, Neema V. Design and analysis of DECODER circuit with source biasing technique for memory array application. TCVLSI (IEEE), 2017, 3(2): 40[14] Amrutur B S. Design and analysis of fast low power SRAMs. PhD Thesis, Stanford University, 1999[15] Deepaksubramanyam B S, Nunez A. Analysis of subthreshold leakage reduction in CMOS digital circuits. Proceedings of the 13th NASA VLSI Symposium, 2007[16] Peiravi A. Current comparison-based domino: new low leakage high-speed domino circuit for wide FanIn gates. IEEE Trans Very Large Scale Integr (VLSI) Syst, 2013, 21(5): 934 doi: 10.1109/TVLSI.2012.2202408[17] Kang S M, Leblebici Y. CMOS digital integrated circuits analysis and design. 3rd ed. Tata Mcgraw Hill Publication, 2003[18] Shah A P, Neema V, Daulatabad S. PVT variations aware low leakage DOIND approach for nanoscale Domino logic circuits. IEEE Power, Communication and Information Technology Conference (PCITC) Siksha ‘O’ Anusandhan University, Bhubaneswar, India, 2015 -
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