REVIEWS

Challenges and opportunities toward fully automated analog layout design

Hao Chen, Mingjie Liu, Xiyuan Tang, Keren Zhu, Nan Sun and David Z. Pan

+ Author Affiliations

 Corresponding author: David Z. Pan, email: dpan@ece.utexas.edu

PDF

Turn off MathJax

Abstract: Realizing the layouts of analog/mixed-signal (AMS) integrated circuits (ICs) is a complicated task due to the high design flexibility and sensitive circuit performance. Compared with the advancements of digital IC layout automation, analog IC layout design is still heavily manual, which leads to a more time-consuming and error-prone process. In recent years, significant progress has been made in automated analog layout design with emerging of several open-source frameworks. This paper firstly reviews the existing state-of-the art AMS layout synthesis frameworks with focus on the different approaches and their individual challenges. We then present recent research trends and opportunities in the field. Finally, we summaries the paper with open questions and future directions for fully-automating the analog IC layout.

Key words: VLSIintegrated circuitASICEDAanalog ic designphysical design



[1]
Rijmenants J, Litsios J B, Schwarz T R, et al. ILAC: An automated layout tool for analog CMOS circuits. IEEE J Solid-State Circuits, 1989, 24(2), 417 doi: 10.1109/4.18603
[2]
Weaver S, Hershberg B, Knierim D, et al. A 6b stochastic flash analog-to-digital converter without calibration or reference ladder. Proc ASSCC, 2008, 373
[3]
Weaver S, Hershberg B, Moon U K. Digitally synthesized stochastic flash ADC using only standard digital cells. IEEE Trans Circuits Syst I, 2013, 61(1), 84 doi: 10.1109/TCSI.2013.2268571
[4]
Fahmy A, Liu J, Kim T, et al. An all-digital scalable and reconfigurable wide-input range stochastic ADC using only standard cells. IEEE TCAS II, 2015, 62(8), 731 doi: 10.1109/TCSII.2015.2415231
[5]
Waters A, Moon U K. A fully automated verilog-to-layout synthesized ADC demonstrating 56 dB-SNDR with 2 MHz-BW. Proc ASSCC, 2015, 1
[6]
Ansari E, Wentzloff D D. A 5 mW 250 MS/s 12-bit synthesized digital to analog converter. Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014, 1
[7]
Liu J, Fahmy A, Kim T, et al. A fully synthesized 0.4 V 77 dB SFDR reprogrammable SRMC filter using digital standard cells. Proc CICC, 2015, 1
[8]
Seo M J, Roh Y J, Chang D J, et al. A reusable code-based SAR ADC design with CDAC compiler and synthesizable analog building blocks. IEEE Trans Circuits Syst II, 2018, 65(12), 1904 doi: 10.1109/TCSII.2018.2822811
[9]
Weaver S, Hershberg B, Maghari N, et al. Domino-logic-based ADC for digital synthesis. IEEE Trans Circuits Syst II, 2011, 58(11), 744 doi: 10.1109/TCSII.2011.2168019
[10]
Park Y, Wentzloff D D. An all-digital PLL synthesized from a digital standard cell library in 65 nm CMOS. 2011 IEEE Custom Integrated Circuits Conference (CICC), 2011, 1
[11]
Deng W, Yang D, Narayanan A T, et al. A 0.048 mm2 3 mW synthesizable fractional-N PLL with a soft injectionlocking technique. ISSCC Digest of Technical Papers, 2015, 1
[12]
Bang S, Lim W, Augustine C, et al. A fully synthesizable distributed and scalable all-digital LDO in 10 nm CMOS. 2020 IEEE International Solid-State Circuits Conference (ISSCC), 2020, 380
[13]
Park Y, Wentzloff D D. An all-digital 12 pJ/pulse IR-UWB transmitter synthesized from a standard cell library. IEEE J Solid-State Circuits, 2011, 46(5), 1147 doi: 10.1109/JSSC.2011.2112232
[14]
Li S, Xu B, Pan D Z, et al. A 60-fJ/step 11-ENOB VCO-based CTDSM synthesized from digital standard cell library. Proc CICC, 2019, 1
[15]
Xu B, Li S, Sun N, et al. A scaling compatible, synthesis friendly VCO-based delta-sigma ADC design and synthesis methodology. Proc DAC, 2017, 1
[16]
IDEA-FASoC project
[17]
Ajayi T, Cherivirala Y, Kwon K, et al. Fully autonomous mixed signal SoC design & layout generation platform. 2020 Hot Chips: A Symposium on High Performance Chips, 2020
[18]
Kobayashi T, Nogami K, Shirotori T, et al. A current-mode latch sense amplifier and a static power saving input buffer for low-power architecture. Symposium on VLSI Circuits Digest of Technical Papers, 1992, 28
[19]
Shim M, Jeong S, Myers P D, et al. Edge-pursuit comparator: An energy-scalable oscillator collapse-based comparator with application in a 74.1 dB SNDR and 20 kS/s 15 b SAR ADC. IEEE J Solid-State Circuits, 2017, 52(4), 1077s doi: 10.1109/JSSC.2016.2631299
[20]
Jung W, Jeong S, Oh S, et al. A 0.7 pF-to-10nF fully digital capacitance-to-digital converter using iterative delay-chain discharge. Proc ISSCC, 2015, 1
[21]
Chen D J, Lee J, Sheu B J. Slam: A smart analog module layout generator for mixed analog-digital VLSI design. Proc ICCD, 1989, 24
[22]
Stefanovic D, Kayal M, Pastre M, et al. Procedural analog design (pad) tool. Proc ISQED, 2003, 313
[23]
Youssef S, Javid F, Dupuis D, et al. A python-based layout-aware analog design methodology for nanometric technologies. IEEE International Design and Test Workshop (IDT), 2011, 62
[24]
Crossley J, Puggelli A, Le H, et al. BAG: A designer-oriented integrated framework for the development of AMS circuit generators. Proc ICCAD, 2013, 74
[25]
Castro-Lopez R, Guerra O, Roca E, et al. An integrated layout-synthesis approach for analog ICs. IEEE TCAD, 2008, 27(7), 1179 doi: 10.1109/TCAD.2008.923417
[26]
Han S, Jeong S, Kim C, et al. GUI-Enhanced layout generation of ffe sst txs for fast high-speed serial link design. Proc DAC, 2020
[27]
Ding M, Harpe P, Chen G, et al. A hybrid design automation tool for sar adcs in IoT. IEEE TVLSI, 2018, 26(12), 2853 doi: 10.1109/TVLSI.2018.2865404
[28]
Wulff C, Ytterdal T. A compiled 9-bit 20-MS/s 3.5-fJ/conv. step SAR ADC in 28-nm FDSOI for bluetooth low energy receivers. IEEE J Solid-State Circuits, 2017, 52(7), 1915 doi: 10.1109/JSSC.2017.2685463
[29]
Chang E, Han J, Bae W, et al. BAG2: A process-portable framework for generator-based ams circuit design. Proc CICC, 2018, 1
[30]
Hakhamaneshi K, Werblun N, Abbeel P, et al. Bagnet: Berkeley analog generator with layout optimizer boosted with deep neural networks. Proc ICCAD, 2019, 1
[31]
Settaluri K, Haj-Ali A, Huang Q, et al. Autockt: Deep reinforcement learning of analog circuit designs. Proc DATE, 2020, 490
[32]
Hammouda S, Said H, Dessouky M, et al. Chameleon art: a non-optimization based analog design migration framework. Proc DAC, 2006, 885
[33]
Pan P, Chin C, Chen H, et al. A fast prototyping framework for analog layout migration with planar preservation. IEEE TCAD, 2015, 34(9), 1373 doi: 10.1109/TCAD.2015.2418312
[34]
Dong X, Zhang L. Process-variation-aware rule-based optical proximity correction for analog layout migration. IEEE TCAD, 2017, 36(8), 1395 doi: 10.1109/TCAD.2016.2626437
[35]
Jangkrajarng N, Zhang L, Bhattacharya S, et al. Template-based parasitic-aware optimization and retargeting of analog and rf integrated circuit layouts. Proc ICCAD, 2006, 342
[36]
Zhang L, Jangkrajarng N, Bhattacharya S, et al. Parasitic-aware optimization and retargeting of analog layouts: A symbolic-template approach. IEEE TCAD, 2008, 27(5), 791 doi: 10.1109/TCAD.2008.917594
[37]
Rutenbar R A. Analog circuit and layout synthesis revisited. Proc ISPD, 2015, 83
[38]
Kunal K, Madhusudan M, Sharma A K, et al. ALIGN: Open-source analog layout automation from the ground up. Proc DAC, 2019, 1
[39]
Xu B, Zhu K, Liu M, et al. MAGICAL: Toward fully automated analog ic layout leveraging human and machine intelligence. Proc ICCAD, 2019, 1
[40]
Cohn J M, Garrod D J, Rutenbar R A, et al. KOAN/ANAGRAM II: New tools for device-level analog placement and routing. IEEE J Solid-State Circuits, 1991, 26(3), 330 doi: 10.1109/4.75012
[41]
Balasa F, Lampaert K. Module placement for analog layout using the sequence-pair representation. Proc DAC, 1999, 274
[42]
Pang Y, Balasa F, Lampaert K, et al. Block placement with symmetry constraints based on the O-tree non-slicing representation. Proc DAC, 2000, 464
[43]
Balasa F, Maruvada S C, Krishnamoorthy K. Efficient solution space exploration based on segment trees in analog placement with symmetry constraints. Proc ICCAD, 2002, 497
[44]
Balasa F, Maruvada S C, Krishnamoorthy K. Using red-black interval trees in device-level analog placement with symmetry constraints. Proc ASPDAC, 2003, 777
[45]
Lin J M, Wu G M, Chang Y W, et al. Placement with symmetry constraints for analog layout design using TCG-S. Proc ASPDAC, 2005, 1135
[46]
Balasa F, Maruvada S C, Krishnamoorthy K. On the exploration of the solution space in analog placement with symmetry constraints. IEEE TCAD, 2006, 23(2), 177 doi: 10.1109/TCAD.2003.822132
[47]
Long D, Hong X, Dong S. Signal-path driven partition and placement for analog circuit. Proc ASPDAC, 2006
[48]
Liu J, Dong S, Ma Y, et al. Thermal-driven symmetry constraint for analog layout with CBL representation. Proc ASPDAC, 2007, 191
[49]
Lin P H, Lin S C. Analog placement based on hierarchical module clustering. Proc DAC, 2008, 50
[50]
Strasser M, Eick M, Gräb H, et al. Deterministic analog circuit placement using hierarchically bounded enumeration and enhanced shape functions. Proc ICCAD, 2008, 306
[51]
Lin P H, Chang Y W, Lin S C. Analog placement based on symmetry-island formulation. IEEE TCAD, 2009, 28(6), 791 doi: 10.1109/tcad.2009.2017433
[52]
Xiao L, Young E F Y. Analog placement with common centroid and 1-D symmetry constraints. Proc ASPDAC, 2009, 353
[53]
Lin P H, Zhang H, Wong M D F, et al. Thermal-driven analog placement considering device matching. Proc DAC, 2009, 593
[54]
Nakatake S, Kawakita M, Ito T, et al. Regularity-oriented analog placement with diffusion sharing and well island generation. Proc ASPDAC, 2010, 305
[55]
Lin C W, Lin J M, Huang C P, et al. Performance-driven analog placement considering boundary constraint. Proc DAC, 2010, 292
[56]
Ma Q, Xiao L, Tam Y C, et al. Simultaneous handling of symmetry, common centroid, and general placement constraints. IEEE TCAD, 2011, 30, 85 doi: 10.1109/TCAD.2010.2064490
[57]
Tsao H F, Chou P Y, Huang S L, et al. A corner stitching compliant b*-tree representation and its applications to analog placement. Proc ICCAD, 2011, 507
[58]
Chou P Y, Ou H C, Chang Y W. Heterogeneous b*-trees for analog placement with symmetry and regularity considerations. Proc ICCAD, 2011, 512
[59]
Lin C W, Lu C C, Lin J M, et al. Routability-driven placement algorithm for analog integrated circuits. Proc ISPD, 2012, 71
[60]
Wu P H, Lin M P H, Chen Y R, et al. Performance-driven analog placement considering monotonic current paths. Proc ICCAD, 2012
[61]
Chien H C C, Ou H C, Chen T C, et al. Double patterning lithography-aware analog placement. Proc DAC, 2013
[62]
Ou H C, Chien H C C, Chang Y W. Simultaneous analog placement and routing with current flow and current density considerations. Proc DAC, 2013
[63]
Wu P H, Lin M P H, Chen T C, et al. Exploring feasibilities of symmetry islands and monotonic current paths in slicing trees for analog placement. IEEE TCAD, 2014, 33(6), 879 doi: 10.1109/TCAD.2014.2305831
[64]
Wu I P, Ou H C, Chang Y W. QB-trees: Towards an optimal topological representation and its applications to analog layout designs. Proc DAC, 2016
[65]
Ou H C, Tseng K H, Liu J Y, et al. Layout-dependent effects-aware analytical analog placement. IEEE TCAD, 2016, 35(8), 1243 doi: 10.1109/TCAD.2015.2501293
[66]
Xu B, Li S, Xu X, et al. Hierarchical and analytical placement techniques for high-performance analog circuits. Proc ISPD, 2017
[67]
Lu Y S, Chang Y H, Chang Y W. WB-trees: A meshed tree representation for FinFET analog layout designs. Proc DAC, 2018
[68]
Patyal A, Pan P C, A A K, et al. Analog placement with current flow and symmetry constraints using PCP-SP. Proc DAC, 2018
[69]
Xu B, Basaran B, Su M, et al. Analog placement constraint extraction and exploration with the application to layout retargeting. Proc ISPD, 2018
[70]
Xu B, Li S, Pui C W, et al. Device layer-aware analytical placement for analog circuits. Proc ISPD, 2019
[71]
Zhu K, Chen H, Liu M, et al. Effective analog/mixed-signal circuit placement considering system signal flow. Proc ICCAD, 2020
[72]
Lampaert K, Gielen G, Sansen W M. A performance-driven placement tool for analog integrated circuits. IEEE J Solid-State Circuits, 1995, 30(7), 773 doi: 10.1109/4.391116
[73]
Li Y, Lin Y, Madhusudan M, et al. Exploring a machine learning approach to performance driven analog IC placement. 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2020, 24
[74]
Li Y, Lin Y, Madhusudan M, et al. A customized graph neural network model for guiding analog IC placement. ICCAD 2020: IEEE/ACM International Conference on Computer-Aided Design, 2020
[75]
Choudhury U, Sangiovanni-Vincentelli A. Constraint-based channel routing for analog and mixed analog/digital circuits. IEEE TCAD, 1993, 12(4), 497 doi: 10.1109/43.229733
[76]
Xiao L, Young E F Y, He X, et al. Practical placement and routing techniques for analog circuit designs. Proc ICCAD, 2010, 675
[77]
Lin J W, Ho T Y, Jiang I H R. Reliability-driven power/ground routing for analog ICs. ACM TODAES, 2019, 17, 1 doi: 10.1145/2071356.2071362
[78]
Chen H, Zhu K, Liu M, et al. Toward silicon-proven detailed routing for analog and mixed-signal circuits. Proc ICCAD, 2020
[79]
Ajayi T, Chhabria V A, Fogaça M, et al. Toward an open-source digital flow: First learnings from the openroad project. Proc DAC, 2019, 76, 1
[80]
Zhu K, Liu M, Lin Y, et al. GeniusRoute: A new analog routing paradigm using generative neural network guidance. Proc ICCAD, 2019, 1
[81]
Liu M, Li W, Zhu K, et al. S3DET: Detecting system symmetry constraints for analog circuits with graph similarity. Proc ASPDAC, 2020, 193
[82]
Liu M, Zhu K, Gu J, et al. Towards decrypting the art of analog layout: Placement quality prediction via transfer learning. Proc DATE, 2020
[83]
Xu B, Lin Y, Tang X, et al. WellGAN: Generative-adversarial-network-guided well generation for analog/mixedsignal circuit layout. Proc DAC, 2019, 1
[84]
Charbon E, Malavasi E, Sangiovanni-Vincentelli A. Generalized constraint generation for analog circuit design. Proc ICCAD, 1993, 408
[85]
Hao Q, Dong S, Chen S, et al. Constraints generation for analog circuits layout. International Conference on Communications, Circuits and Systems, 2004, 2, 1339 doi: 10.1109/ICCCAS.2004.1346419
[86]
Zhou Z, Dong S, Hong X, et al. Analog constraints extraction based on the signal flow analysis. International Conference on ASIC, 2005, 2, 825 doi: 10.1109/ICASIC.2005.1611454
[87]
Wu P, Lin M P, Ho T. Analog layout synthesis with knowledge mining. 2015 European Conference on Circuit Theory and Design (ECCTD), 2015, 1 doi: 10.1109/ECCTD.2015.7300111
[88]
Eick M, Strasser M, Lu K, et al. Comprehensive generation of hierarchical placement rules for analog integrated circuits. IEEE TCAD, 2011, 30(2), 180 doi: 10.1109/TCAD.2010.2097172
[89]
Kunal K, Poojary P, Dhar T, et al. A general approach for identifying hierarchical symmetry constraints for analog circuit layout. Proc ICCAD, 2020
[90]
Kunal K, Dhar T, Madhusudan M, et al. GANA: Graph convolutional network based automated netlist annotation for analog circuits. Proc DATE, 2020
[91]
Liu M, Zhu K, Tang X, et al. Closing the design loop: Bayesian optimization assisted hierarchical analog layout synthesis. Proc DAC, 2020
[92]
Chen H, Liu M, Xu B, et al. Magical: An open-source fully automated analog IC layout system from netlist to GDSII. IEEE Design & Test, 2020
[93]
Ajayi T, Chhabria V A, Fogaça M, et al. Toward an open-source digital flow: First learnings from the openroad project. Proc DAC, 2019
[94]
Lin C W, Lee C L, Lin J M, et al. Analytical-based approach for capacitor placement with gradient error compensation and device correlation enhancement in analog integrated circuits. Proc ICCAD, 2012
Fig. 1.  (Color online) Synthesis-friendly analog circuits design flow.

Fig. 2.  (Color online) Procedural analog circuits layout design flow.

Fig. 3.  (Color online) An example of the Python script and generated layout of BAG2[16].

Fig. 4.  (Color online) Optimization-based layout design flow.

Fig. 5.  (Color online) Examples of placement constraints. (a) Symmetry constraint. (b) Common-centroid constraint.

Fig. 6.  The overall flow of MAGICAL[39].

Fig. 7.  (Color online) Layout generator with layout performance prediction.

Fig. 8.  (Color online) A flow for learning knowledge from manual layouts.

Fig. 9.  GeniusRoute framwork. (a) Training phase. (b) Inference phase[80].

Fig. 10.  A flow with in-loop simulation.

[1]
Rijmenants J, Litsios J B, Schwarz T R, et al. ILAC: An automated layout tool for analog CMOS circuits. IEEE J Solid-State Circuits, 1989, 24(2), 417 doi: 10.1109/4.18603
[2]
Weaver S, Hershberg B, Knierim D, et al. A 6b stochastic flash analog-to-digital converter without calibration or reference ladder. Proc ASSCC, 2008, 373
[3]
Weaver S, Hershberg B, Moon U K. Digitally synthesized stochastic flash ADC using only standard digital cells. IEEE Trans Circuits Syst I, 2013, 61(1), 84 doi: 10.1109/TCSI.2013.2268571
[4]
Fahmy A, Liu J, Kim T, et al. An all-digital scalable and reconfigurable wide-input range stochastic ADC using only standard cells. IEEE TCAS II, 2015, 62(8), 731 doi: 10.1109/TCSII.2015.2415231
[5]
Waters A, Moon U K. A fully automated verilog-to-layout synthesized ADC demonstrating 56 dB-SNDR with 2 MHz-BW. Proc ASSCC, 2015, 1
[6]
Ansari E, Wentzloff D D. A 5 mW 250 MS/s 12-bit synthesized digital to analog converter. Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014, 1
[7]
Liu J, Fahmy A, Kim T, et al. A fully synthesized 0.4 V 77 dB SFDR reprogrammable SRMC filter using digital standard cells. Proc CICC, 2015, 1
[8]
Seo M J, Roh Y J, Chang D J, et al. A reusable code-based SAR ADC design with CDAC compiler and synthesizable analog building blocks. IEEE Trans Circuits Syst II, 2018, 65(12), 1904 doi: 10.1109/TCSII.2018.2822811
[9]
Weaver S, Hershberg B, Maghari N, et al. Domino-logic-based ADC for digital synthesis. IEEE Trans Circuits Syst II, 2011, 58(11), 744 doi: 10.1109/TCSII.2011.2168019
[10]
Park Y, Wentzloff D D. An all-digital PLL synthesized from a digital standard cell library in 65 nm CMOS. 2011 IEEE Custom Integrated Circuits Conference (CICC), 2011, 1
[11]
Deng W, Yang D, Narayanan A T, et al. A 0.048 mm2 3 mW synthesizable fractional-N PLL with a soft injectionlocking technique. ISSCC Digest of Technical Papers, 2015, 1
[12]
Bang S, Lim W, Augustine C, et al. A fully synthesizable distributed and scalable all-digital LDO in 10 nm CMOS. 2020 IEEE International Solid-State Circuits Conference (ISSCC), 2020, 380
[13]
Park Y, Wentzloff D D. An all-digital 12 pJ/pulse IR-UWB transmitter synthesized from a standard cell library. IEEE J Solid-State Circuits, 2011, 46(5), 1147 doi: 10.1109/JSSC.2011.2112232
[14]
Li S, Xu B, Pan D Z, et al. A 60-fJ/step 11-ENOB VCO-based CTDSM synthesized from digital standard cell library. Proc CICC, 2019, 1
[15]
Xu B, Li S, Sun N, et al. A scaling compatible, synthesis friendly VCO-based delta-sigma ADC design and synthesis methodology. Proc DAC, 2017, 1
[16]
IDEA-FASoC project
[17]
Ajayi T, Cherivirala Y, Kwon K, et al. Fully autonomous mixed signal SoC design & layout generation platform. 2020 Hot Chips: A Symposium on High Performance Chips, 2020
[18]
Kobayashi T, Nogami K, Shirotori T, et al. A current-mode latch sense amplifier and a static power saving input buffer for low-power architecture. Symposium on VLSI Circuits Digest of Technical Papers, 1992, 28
[19]
Shim M, Jeong S, Myers P D, et al. Edge-pursuit comparator: An energy-scalable oscillator collapse-based comparator with application in a 74.1 dB SNDR and 20 kS/s 15 b SAR ADC. IEEE J Solid-State Circuits, 2017, 52(4), 1077s doi: 10.1109/JSSC.2016.2631299
[20]
Jung W, Jeong S, Oh S, et al. A 0.7 pF-to-10nF fully digital capacitance-to-digital converter using iterative delay-chain discharge. Proc ISSCC, 2015, 1
[21]
Chen D J, Lee J, Sheu B J. Slam: A smart analog module layout generator for mixed analog-digital VLSI design. Proc ICCD, 1989, 24
[22]
Stefanovic D, Kayal M, Pastre M, et al. Procedural analog design (pad) tool. Proc ISQED, 2003, 313
[23]
Youssef S, Javid F, Dupuis D, et al. A python-based layout-aware analog design methodology for nanometric technologies. IEEE International Design and Test Workshop (IDT), 2011, 62
[24]
Crossley J, Puggelli A, Le H, et al. BAG: A designer-oriented integrated framework for the development of AMS circuit generators. Proc ICCAD, 2013, 74
[25]
Castro-Lopez R, Guerra O, Roca E, et al. An integrated layout-synthesis approach for analog ICs. IEEE TCAD, 2008, 27(7), 1179 doi: 10.1109/TCAD.2008.923417
[26]
Han S, Jeong S, Kim C, et al. GUI-Enhanced layout generation of ffe sst txs for fast high-speed serial link design. Proc DAC, 2020
[27]
Ding M, Harpe P, Chen G, et al. A hybrid design automation tool for sar adcs in IoT. IEEE TVLSI, 2018, 26(12), 2853 doi: 10.1109/TVLSI.2018.2865404
[28]
Wulff C, Ytterdal T. A compiled 9-bit 20-MS/s 3.5-fJ/conv. step SAR ADC in 28-nm FDSOI for bluetooth low energy receivers. IEEE J Solid-State Circuits, 2017, 52(7), 1915 doi: 10.1109/JSSC.2017.2685463
[29]
Chang E, Han J, Bae W, et al. BAG2: A process-portable framework for generator-based ams circuit design. Proc CICC, 2018, 1
[30]
Hakhamaneshi K, Werblun N, Abbeel P, et al. Bagnet: Berkeley analog generator with layout optimizer boosted with deep neural networks. Proc ICCAD, 2019, 1
[31]
Settaluri K, Haj-Ali A, Huang Q, et al. Autockt: Deep reinforcement learning of analog circuit designs. Proc DATE, 2020, 490
[32]
Hammouda S, Said H, Dessouky M, et al. Chameleon art: a non-optimization based analog design migration framework. Proc DAC, 2006, 885
[33]
Pan P, Chin C, Chen H, et al. A fast prototyping framework for analog layout migration with planar preservation. IEEE TCAD, 2015, 34(9), 1373 doi: 10.1109/TCAD.2015.2418312
[34]
Dong X, Zhang L. Process-variation-aware rule-based optical proximity correction for analog layout migration. IEEE TCAD, 2017, 36(8), 1395 doi: 10.1109/TCAD.2016.2626437
[35]
Jangkrajarng N, Zhang L, Bhattacharya S, et al. Template-based parasitic-aware optimization and retargeting of analog and rf integrated circuit layouts. Proc ICCAD, 2006, 342
[36]
Zhang L, Jangkrajarng N, Bhattacharya S, et al. Parasitic-aware optimization and retargeting of analog layouts: A symbolic-template approach. IEEE TCAD, 2008, 27(5), 791 doi: 10.1109/TCAD.2008.917594
[37]
Rutenbar R A. Analog circuit and layout synthesis revisited. Proc ISPD, 2015, 83
[38]
Kunal K, Madhusudan M, Sharma A K, et al. ALIGN: Open-source analog layout automation from the ground up. Proc DAC, 2019, 1
[39]
Xu B, Zhu K, Liu M, et al. MAGICAL: Toward fully automated analog ic layout leveraging human and machine intelligence. Proc ICCAD, 2019, 1
[40]
Cohn J M, Garrod D J, Rutenbar R A, et al. KOAN/ANAGRAM II: New tools for device-level analog placement and routing. IEEE J Solid-State Circuits, 1991, 26(3), 330 doi: 10.1109/4.75012
[41]
Balasa F, Lampaert K. Module placement for analog layout using the sequence-pair representation. Proc DAC, 1999, 274
[42]
Pang Y, Balasa F, Lampaert K, et al. Block placement with symmetry constraints based on the O-tree non-slicing representation. Proc DAC, 2000, 464
[43]
Balasa F, Maruvada S C, Krishnamoorthy K. Efficient solution space exploration based on segment trees in analog placement with symmetry constraints. Proc ICCAD, 2002, 497
[44]
Balasa F, Maruvada S C, Krishnamoorthy K. Using red-black interval trees in device-level analog placement with symmetry constraints. Proc ASPDAC, 2003, 777
[45]
Lin J M, Wu G M, Chang Y W, et al. Placement with symmetry constraints for analog layout design using TCG-S. Proc ASPDAC, 2005, 1135
[46]
Balasa F, Maruvada S C, Krishnamoorthy K. On the exploration of the solution space in analog placement with symmetry constraints. IEEE TCAD, 2006, 23(2), 177 doi: 10.1109/TCAD.2003.822132
[47]
Long D, Hong X, Dong S. Signal-path driven partition and placement for analog circuit. Proc ASPDAC, 2006
[48]
Liu J, Dong S, Ma Y, et al. Thermal-driven symmetry constraint for analog layout with CBL representation. Proc ASPDAC, 2007, 191
[49]
Lin P H, Lin S C. Analog placement based on hierarchical module clustering. Proc DAC, 2008, 50
[50]
Strasser M, Eick M, Gräb H, et al. Deterministic analog circuit placement using hierarchically bounded enumeration and enhanced shape functions. Proc ICCAD, 2008, 306
[51]
Lin P H, Chang Y W, Lin S C. Analog placement based on symmetry-island formulation. IEEE TCAD, 2009, 28(6), 791 doi: 10.1109/tcad.2009.2017433
[52]
Xiao L, Young E F Y. Analog placement with common centroid and 1-D symmetry constraints. Proc ASPDAC, 2009, 353
[53]
Lin P H, Zhang H, Wong M D F, et al. Thermal-driven analog placement considering device matching. Proc DAC, 2009, 593
[54]
Nakatake S, Kawakita M, Ito T, et al. Regularity-oriented analog placement with diffusion sharing and well island generation. Proc ASPDAC, 2010, 305
[55]
Lin C W, Lin J M, Huang C P, et al. Performance-driven analog placement considering boundary constraint. Proc DAC, 2010, 292
[56]
Ma Q, Xiao L, Tam Y C, et al. Simultaneous handling of symmetry, common centroid, and general placement constraints. IEEE TCAD, 2011, 30, 85 doi: 10.1109/TCAD.2010.2064490
[57]
Tsao H F, Chou P Y, Huang S L, et al. A corner stitching compliant b*-tree representation and its applications to analog placement. Proc ICCAD, 2011, 507
[58]
Chou P Y, Ou H C, Chang Y W. Heterogeneous b*-trees for analog placement with symmetry and regularity considerations. Proc ICCAD, 2011, 512
[59]
Lin C W, Lu C C, Lin J M, et al. Routability-driven placement algorithm for analog integrated circuits. Proc ISPD, 2012, 71
[60]
Wu P H, Lin M P H, Chen Y R, et al. Performance-driven analog placement considering monotonic current paths. Proc ICCAD, 2012
[61]
Chien H C C, Ou H C, Chen T C, et al. Double patterning lithography-aware analog placement. Proc DAC, 2013
[62]
Ou H C, Chien H C C, Chang Y W. Simultaneous analog placement and routing with current flow and current density considerations. Proc DAC, 2013
[63]
Wu P H, Lin M P H, Chen T C, et al. Exploring feasibilities of symmetry islands and monotonic current paths in slicing trees for analog placement. IEEE TCAD, 2014, 33(6), 879 doi: 10.1109/TCAD.2014.2305831
[64]
Wu I P, Ou H C, Chang Y W. QB-trees: Towards an optimal topological representation and its applications to analog layout designs. Proc DAC, 2016
[65]
Ou H C, Tseng K H, Liu J Y, et al. Layout-dependent effects-aware analytical analog placement. IEEE TCAD, 2016, 35(8), 1243 doi: 10.1109/TCAD.2015.2501293
[66]
Xu B, Li S, Xu X, et al. Hierarchical and analytical placement techniques for high-performance analog circuits. Proc ISPD, 2017
[67]
Lu Y S, Chang Y H, Chang Y W. WB-trees: A meshed tree representation for FinFET analog layout designs. Proc DAC, 2018
[68]
Patyal A, Pan P C, A A K, et al. Analog placement with current flow and symmetry constraints using PCP-SP. Proc DAC, 2018
[69]
Xu B, Basaran B, Su M, et al. Analog placement constraint extraction and exploration with the application to layout retargeting. Proc ISPD, 2018
[70]
Xu B, Li S, Pui C W, et al. Device layer-aware analytical placement for analog circuits. Proc ISPD, 2019
[71]
Zhu K, Chen H, Liu M, et al. Effective analog/mixed-signal circuit placement considering system signal flow. Proc ICCAD, 2020
[72]
Lampaert K, Gielen G, Sansen W M. A performance-driven placement tool for analog integrated circuits. IEEE J Solid-State Circuits, 1995, 30(7), 773 doi: 10.1109/4.391116
[73]
Li Y, Lin Y, Madhusudan M, et al. Exploring a machine learning approach to performance driven analog IC placement. 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2020, 24
[74]
Li Y, Lin Y, Madhusudan M, et al. A customized graph neural network model for guiding analog IC placement. ICCAD 2020: IEEE/ACM International Conference on Computer-Aided Design, 2020
[75]
Choudhury U, Sangiovanni-Vincentelli A. Constraint-based channel routing for analog and mixed analog/digital circuits. IEEE TCAD, 1993, 12(4), 497 doi: 10.1109/43.229733
[76]
Xiao L, Young E F Y, He X, et al. Practical placement and routing techniques for analog circuit designs. Proc ICCAD, 2010, 675
[77]
Lin J W, Ho T Y, Jiang I H R. Reliability-driven power/ground routing for analog ICs. ACM TODAES, 2019, 17, 1 doi: 10.1145/2071356.2071362
[78]
Chen H, Zhu K, Liu M, et al. Toward silicon-proven detailed routing for analog and mixed-signal circuits. Proc ICCAD, 2020
[79]
Ajayi T, Chhabria V A, Fogaça M, et al. Toward an open-source digital flow: First learnings from the openroad project. Proc DAC, 2019, 76, 1
[80]
Zhu K, Liu M, Lin Y, et al. GeniusRoute: A new analog routing paradigm using generative neural network guidance. Proc ICCAD, 2019, 1
[81]
Liu M, Li W, Zhu K, et al. S3DET: Detecting system symmetry constraints for analog circuits with graph similarity. Proc ASPDAC, 2020, 193
[82]
Liu M, Zhu K, Gu J, et al. Towards decrypting the art of analog layout: Placement quality prediction via transfer learning. Proc DATE, 2020
[83]
Xu B, Lin Y, Tang X, et al. WellGAN: Generative-adversarial-network-guided well generation for analog/mixedsignal circuit layout. Proc DAC, 2019, 1
[84]
Charbon E, Malavasi E, Sangiovanni-Vincentelli A. Generalized constraint generation for analog circuit design. Proc ICCAD, 1993, 408
[85]
Hao Q, Dong S, Chen S, et al. Constraints generation for analog circuits layout. International Conference on Communications, Circuits and Systems, 2004, 2, 1339 doi: 10.1109/ICCCAS.2004.1346419
[86]
Zhou Z, Dong S, Hong X, et al. Analog constraints extraction based on the signal flow analysis. International Conference on ASIC, 2005, 2, 825 doi: 10.1109/ICASIC.2005.1611454
[87]
Wu P, Lin M P, Ho T. Analog layout synthesis with knowledge mining. 2015 European Conference on Circuit Theory and Design (ECCTD), 2015, 1 doi: 10.1109/ECCTD.2015.7300111
[88]
Eick M, Strasser M, Lu K, et al. Comprehensive generation of hierarchical placement rules for analog integrated circuits. IEEE TCAD, 2011, 30(2), 180 doi: 10.1109/TCAD.2010.2097172
[89]
Kunal K, Poojary P, Dhar T, et al. A general approach for identifying hierarchical symmetry constraints for analog circuit layout. Proc ICCAD, 2020
[90]
Kunal K, Dhar T, Madhusudan M, et al. GANA: Graph convolutional network based automated netlist annotation for analog circuits. Proc DATE, 2020
[91]
Liu M, Zhu K, Tang X, et al. Closing the design loop: Bayesian optimization assisted hierarchical analog layout synthesis. Proc DAC, 2020
[92]
Chen H, Liu M, Xu B, et al. Magical: An open-source fully automated analog IC layout system from netlist to GDSII. IEEE Design & Test, 2020
[93]
Ajayi T, Chhabria V A, Fogaça M, et al. Toward an open-source digital flow: First learnings from the openroad project. Proc DAC, 2019
[94]
Lin C W, Lee C L, Lin J M, et al. Analytical-based approach for capacitor placement with gradient error compensation and device correlation enhancement in analog integrated circuits. Proc ICCAD, 2012
  • Search

    Advanced Search >>

    GET CITATION

    shu

    Export: BibTex EndNote

    Article Metrics

    Article views: 3757 Times PDF downloads: 145 Times Cited by: 0 Times

    History

    Received: 18 July 2020 Revised: 22 September 2020 Online: Accepted Manuscript: 10 October 2020Uncorrected proof: 12 October 2020Published: 03 November 2020

    Catalog

      Email This Article

      User name:
      Email:*请输入正确邮箱
      Code:*验证码错误
      Hao Chen, Mingjie Liu, Xiyuan Tang, Keren Zhu, Nan Sun, David Z. Pan. Challenges and opportunities toward fully automated analog layout design[J]. Journal of Semiconductors, 2020, 41(11): 111407. doi: 10.1088/1674-4926/41/11/111407 H Chen, M J Liu, X Y Tang, K R Zhu, N Sun, David Z. Pan, Challenges and opportunities toward fully automated analog layout design[J]. J. Semicond., 2020, 41(11): 111407. doi: 10.1088/1674-4926/41/11/111407.Export: BibTex EndNote
      Citation:
      Hao Chen, Mingjie Liu, Xiyuan Tang, Keren Zhu, Nan Sun, David Z. Pan. Challenges and opportunities toward fully automated analog layout design[J]. Journal of Semiconductors, 2020, 41(11): 111407. doi: 10.1088/1674-4926/41/11/111407

      H Chen, M J Liu, X Y Tang, K R Zhu, N Sun, David Z. Pan, Challenges and opportunities toward fully automated analog layout design[J]. J. Semicond., 2020, 41(11): 111407. doi: 10.1088/1674-4926/41/11/111407.
      Export: BibTex EndNote

      Challenges and opportunities toward fully automated analog layout design

      doi: 10.1088/1674-4926/41/11/111407
      More Information
      • Corresponding author: email: dpan@ece.utexas.edu
      • Received Date: 2020-07-18
      • Revised Date: 2020-09-22
      • Published Date: 2020-11-10

      Catalog

        /

        DownLoad:  Full-Size Img  PowerPoint
        Return
        Return