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The past and future of multi-gate field-effect transistors: Process challenges and reliability issues

Ying Sun1, Xiao Yu2, Rui Zhang1, Bing Chen1 and Ran Cheng1,

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 Corresponding author: Ran Cheng, chengran@zju.edu.cn

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Abstract: This work reviews the state-of-the art multi-gate field-effect transistor (MuGFET) process technologies and compares the device performance and reliability characteristics of the MuGFETs with the planar Si CMOS devices. Owing to the 3D wrapped gate structure, MuGFETs can suppress the SCEs and improve the ON-current performance due to the volume inversion of the channel region. As the Si CMOS technology pioneers to sub-10 nm nodes, the process challenges in terms of lithography capability, process integration controversies, performance variability etc. were also discussed in this work. Due to the severe self-heating effect in the MuGFETs, the ballistic transport and reliability characteristics were investigated. Future alternatives for the current Si MuGFET technology were discussed at the end of the paper. More work needs to be done to realize novel high mobility channel MuGFETs with better performance and reliability.

Key words: Si FinFETsballistic transporthigh mobilitybias-temperature instabilityhot-carrier injectiongermanium



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Fig. 1.  (a–f) Schematics of MuGFETs with different gate geometries: (a) IMEC’s gate-all-around (GAA) MOSFET[14], (b) the world-first FinFET[8], (c) IBM’s double-gate (DG) FinFET[11], (d) STMicroelectronics’s GAA MOSFET[15], (e) Intel’s tri-gate FinFET[10], (f) TSMC’s nanowire FinFET[16]. (g–i) TEM images showing the cross-sectional view of fins/nanowires from early works: (g) IBM’s DG FinFET[11], (h) Intel’s tri-gate FinFET[10], (i) Samsung’s nanowire MOSFET[17], (j) IME’s nanowire GAA MOSFET[18], (k) TSMC’s FinFET[27], (l) STMicroelectronics’s GAA MOSFET[28].

Fig. 2.  (Color online) Evolution of MuGFETs from the planar device to the stacking structures. (a) Planar MOSFET. (b) Double-gate (DG) fully depleted SOI MOSFET. (c) FinFET. (d) Ω-gate MOSFET. (e) GAA NW MOSFET. (f) GAA multilayer nanosheet MOSFET.

Fig. 3.  (Color online) DIBL performance as a function of gate length among FDSOI, FinFET and planar technologies[29].

Fig. 4.  (Color online) Comparison of DIBL from ETSOI, DG, tri-gate, and GAA technologies as effective channel length reduces. Data are obtained from IBM and Intel Corp[30, 31].

Fig. 5.  (Color online) ION–DIBL characteristics for MuGFETs with various technologies. As DIBL is a direct indicator of SCE suppression, devices with higher ION and lower DIBL suggests a better electrostatic performance[11, 1719, 3139].

Fig. 6.  (Color online) Thermal resistivity Rth of Si fins for 14, 10 and 7 nm technology nodes as (a) the number of fins varies and (b) the fin height/aspect ratio changes[46, 47].

Fig. 7.  (Color online) Thermal conductivity for various materials used in gate stack, source/drain, channel, isolation and interconnects in a MuGFET. The conductivity reduces as the technology node shrinks. Higher mobility channel materials like Ge and SiGe also exhibit lower thermal conductivity[4852].

Fig. 8.  IDVG characteristics of a Si FinFET measured at drain voltage VD = 1.0 V illustrated in both logarithm (left) and linear (right) scales. The threshold voltage is taken by constant current method while IDsat is taken as the drain current at VG = VTsat + 1.0 V[24].

Fig. 9.  (Color online) (a) The schematic illustration of a pulsed IV testing system for a MOSFET. Pulsed signals are input at the gate electrode and sensed at the drain electrode while the source electrode is kept ground[24, 25]. (b) The waveform of VG used for the IDVG characterization. (c) IDVG characteristics of a Si FinFET (LG = 80 nm) measured at VD = 1.0 V, using pulse measurement with various pulse widths[24].

Fig. 10.  (a) Total resistance RTotal = VD/ID at VD = 50 mV as a function of VG at various characterization temperature. The experimental data (dots) fits well with the resistance model (lines)[24]. (b) Corrected λo/lo ratio for FinFETs at LG ranging from ~20 to ~150 nm, measured by both DC and pulsed I–V methods[24].

Fig. 11.  A summary of 1/Bsat as a function of LG for Si FinFETs, GeOI FETs and FDSOI/UTB FETs. Experimentally extracted Bsat before and after RSD correction, with and without SHE are provided for comparison with the simulated curves[24, 25].

Fig. 12.  (Color online) The change of interface trap density ΔNit as the fin density and VD increase for bulk FinFETs. The stress time tstress is 1000 s[23].

Fig. 13.  (Color online) Aging contribution from NBTI, PBTI, NHCD, and PHCD are compared for 14 and 10 nm technology nodes. Since the improvement in NBTI from 14 to 10 nm node could compensate the aggravation of HCD for both p- and n-FinFETs, the end-of-line (EOL) drive for the 10 nm node actually improves by 1.65 times[45].

Fig. 14.  (Color online) Comparison of SS and ION/Ioff ratio at various LG for MuGFETs with novel high-mobility channels[7683].

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    Received: 19 January 2021 Revised: 31 January 2021 Online: Accepted Manuscript: 01 February 2021Uncorrected proof: 03 February 2021Published: 08 February 2021

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      Ying Sun, Xiao Yu, Rui Zhang, Bing Chen, Ran Cheng. The past and future of multi-gate field-effect transistors: Process challenges and reliability issues[J]. Journal of Semiconductors, 2021, 42(2): 023102. doi: 10.1088/1674-4926/42/2/023102 Y Sun, X Yu, R Zhang, B Chen, R Cheng, The past and future of multi-gate field-effect transistors: Process challenges and reliability issues[J]. J. Semicond., 2021, 42(2): 023102. doi: 10.1088/1674-4926/42/2/023102.Export: BibTex EndNote
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      Ying Sun, Xiao Yu, Rui Zhang, Bing Chen, Ran Cheng. The past and future of multi-gate field-effect transistors: Process challenges and reliability issues[J]. Journal of Semiconductors, 2021, 42(2): 023102. doi: 10.1088/1674-4926/42/2/023102

      Y Sun, X Yu, R Zhang, B Chen, R Cheng, The past and future of multi-gate field-effect transistors: Process challenges and reliability issues[J]. J. Semicond., 2021, 42(2): 023102. doi: 10.1088/1674-4926/42/2/023102.
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      The past and future of multi-gate field-effect transistors: Process challenges and reliability issues

      doi: 10.1088/1674-4926/42/2/023102
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      • Author Bio:

        Ying Sun received the B.S degree in Hefei University of Technology in 2018. She is currently a Ph.D candidate with the College of Micro-Nano Electronics, Zhejiang University. Her research focuses on the device characterization and reliability analysis for advanced CMOS transistors

        Ran Cheng received the B.Eng. and Ph.D degrees in Electrical Engineering from National University of Singapore, Singapore in 2009 and 2014, respectively. From late 2014, she joined Zhejiang University. Her research interests include strain engineering, device modelling, fast and cyrogenic characterization for advanced transistors. She has authored and co-authored over 50 publications. She is currently an Associate Professor with School of Micro-Nano Electronics, Zhejiang University, China

      • Corresponding author: chengran@zju.edu.cn
      • Received Date: 2021-01-19
      • Revised Date: 2021-01-31
      • Published Date: 2021-02-10

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