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A review of silicon-based wafer bonding processes, an approach to realize the monolithic integration of Si-CMOS and III–V-on-Si wafers

Shuyu Bao1, , , Yue Wang1, , Khaw Lina1, Li Zhang1, Bing Wang1, 2, , Wardhana Aji Sasangka1, Kenneth Eng Kian Lee1, Soo Jin Chua1, 3, Jurgen Michel1, 4, Eugene Fitzgerald1, 5, Chuan Seng Tan1, 6 and Kwang Hong Lee1,

+ Author Affiliations

 Corresponding author: Shuyu Bao, shuyu@smart.mit.edu; Bing Wang, wangb266@mail.sysu.edu.cn; Kwang Hong Lee, leek0046@e.ntu.edu.sg

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Abstract: The heterogeneous integration of III–V devices with Si-CMOS on a common Si platform has shown great promise in the new generations of electrical and optical systems for novel applications, such as HEMT or LED with integrated control circuitry. For heterogeneous integration, direct wafer bonding (DWB) techniques can overcome the materials and thermal mismatch issues by directly bonding dissimilar materials systems and device structures together. In addition, DWB can perform at wafer-level, which eases the requirements for integration alignment and increases the scalability for volume production. In this paper, a brief review of the different bonding technologies is discussed. After that, three main DWB techniques of single-, double- and multi-bonding are presented with the demonstrations of various heterogeneous integration applications. Meanwhile, the integration challenges, such as micro-defects, surface roughness and bonding yield are discussed in detail.

Key words: materialthin filmintegrated circuit



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Fig. 1.  Schematic views of (a) silicon–glass anodic bonding and (b) silicon–silicon anodic bonding mediated with a borosilicate glass layer.

Fig. 2.  (Color online) (a) Schematic of the DWB process via SiO2 dielectric layers, and (b) shows the IR image of the bonded wafer.

Fig. 3.  IR images of a bonded wafer with SiO2 dielectric layers (a) as bonded, and (b) after post-bond annealing.

Fig. 4.  (Color online) (a) Schematic of the bonding process with an additional thin deposited SixNy layer, and the IR images of (b) as-bonded wafers and (c) after post-bond annealing.

Fig. 5.  (Color online) The comparison of FTIR spectral changes at the vibration mode at 3750 cm–1 between the SiOx + SixNy and SiO2 films after annealing and four-day storage under cleanroom environments.

Fig. 6.  Change in the SixNy layers stress profile. Compressive stress turns into tensile stress in SixNy layers after annealing, and its stress and bow stay stable after 10 days of storage, indicating that the moisture absorption is blocked.

Fig. 7.  (Color online) (a) Schematic of AlN to AlN bonding process and the IR images of (b) as-bonded wafers, and (c) after post-bond annealing.

Fig. 8.  (Color online) XPS Atomic concentration profiles of pre-annealed AlN.

Fig. 9.  (Color online) Schematic of Al2O3 to Al2O3 bonding process.

Fig. 10.  Cross-sectional TEM images of (a) the bonded wafer pair, and (b) the bonding interface.

Fig. 11.  (Color online) Schematics of Ge-OI fabrication process.

Fig. 12.  Plan view TEM images of the Ge surface of Ge-OI before and after O2 annealing.

Fig. 13.  The EPD determined TDD of the Ge of Ge-OI before annealing and after annealing + CMP.

Fig. 14.  (Color online) Raman spectroscopy of the Ge film on Ge-OI before and after annealing.

Fig. 15.  (Color online) The fabricated 200 mm Ge-OI, GaAs-OI and GaN-OI substrate wafers.

Fig. 16.  (Color online) Schematic flow of the double bonding and layer transfer process.

Fig. 17.  (Color online) (a) Schematic flow of the first bonding process between SOI and thermally oxidized Si handle wafer and (b) IR image of the bonded wafer pair.

Fig. 18.  (Color online) (a) Schematic flow of the first bonding and substrate removal and (b) optical image of the bonded pair after substrate removal where pin-holes are observed.

Fig. 19.  (Color online) Schematic flow of the double bonding process. (a) IR image of bonded SOI–InGaAs pair and (b) IR image of bonded SOI–GaN pair.

Fig. 20.  (Color online) (a) Schematic flow of 1st bonding with CMP-ed BOX layer. (b) Optical image of the resultant wafer after the process, where pin-holes are observed.

Fig. 21.  (Color online) (a) Schematic flow of the double bonding process with additional SiO2 layers. (b) IR image of the bonded wafer pair.

Fig. 22.  (Color online) (a) Schematic flow of double bonding process with BOX layer completely replaced by PECVD oxide. (b) IR image of the bonded pair. No pin-holes are observed.

Fig. 23.  (Color online) IR images and optical images of wafers after double bonding and layer transfer using different methods.

Fig. 24.  Cross-sectional bright field TEM images of the bonded SOI-Si wafer pairs. (a) The overall view and (b) the bonding interface between PECVD oxide and Si prime wafer.

Fig. 25.  (Color online) (a) Updated schematic diagram of the double bonding and layer transfer process. (b) IR image and (c) optical image of the resultant SOI–III–V/Si integrated wafer.

Fig. 26.  Cross-sectional TEM image of the Si-CMOS/III–V/Si wafer after double bond and layer transfer.

Fig. 27.  (Color online) Symmetric (004) reciprocal space map (RSM) of an AlInGaP LED structure measured from XRD (a) before and (b) after bonding with Si-CMOS. Asymmetric (224) RSM of the AlInGaP LED structure (c) before and (d) after bonding with Si-CMOS.

Fig. 28.  (Color online) Schematic flow of replacing Si (111) substrate by Si (001) substrate for GaN HEMT/LED wafer.

Fig. 29.  IR image of a bonded GaN/Si wafer pair after substrate replacement.

Fig. 30.  (Color online) Schematic flow of the diamond CMP process. (a) After oxide deposition, (b) after CMP using slurry with the addition of diamond particles, and (c) another oxide deposition and CMP processes to smoothen the oxide surface which was roughened from the previous step.

Fig. 31.  (a) IR image, (b) optical image of Si-CMOS and GaN LED bonded pair on Si (001) substrate.

Fig. 32.  (Color online) Schematic of the process flow to realize the GaN LED on quartz substrate. (a) A GaN LED epitaxial film on a Si (111) substrate. (b) First wafer bonding between the GaN LED on Si (111) and a Si handle wafers. (c) Removal of the Si (111) substrate. (d) Deposition of SiO2 and Si3N4 layers. (e) Second wafer bonding between the GaN LED-containing handle and a quartz substrate. (f) GaN LED on quartz substrate is realized by releasing the Si handle wafer.

Fig. 33.  (Color online) (a) IR image of a bonded GaN LED/Si (111) substrate and a Si handle wafer after step Fig. 32(b). (b) Photograph of the GaN LED layers temporarily attached to the Si handle wafer after Si (111) substrate removal, step Fig. 32(c). (c) IR image of the bonded GaN LED layers containing Si handle wafer and a quartz substrate after step Fig. 32(e). (d) Photograph of the GaN LED transferred to the quartz substrate, step Fig. 32(f).

Fig. 34.  SEM image of the cross-sectional view of the bonded GaN LED on the quartz substrate.

Fig. 35.  (Color online) Light-up photo of the GaN LED devices on (a) Si and (b) quartz substrates.

Fig. 36.  (Color online) Schematic flow of the multi-bonding and layer transfer process for integration of Si-CMOS and GaAs and GaN together on a common 200 mm Si platform.

Fig. 37.  (Color online) IR image of (a) the first bonding between SOI and Si handle wafer, (b) the second bonding between the SOI-handle and the GaAs/Ge/Si substrate, (c) the third bonding between the GaAs/Ge-SOI-handle and the GaN/Si substrate, and (d) optical image of the SOI-GaAs/Ge/GaN/Si substrate after the triple-bond process. The red circle indicates the defects from the backside of the wafer during TMAH etching caused by the poor adhesion of the protective layer, not affecting the bonding quality.

Fig. 38.  The cross-sectional TEM of the SOI–GaAs/Ge/GaN/Si stack after the triple-bonding and layer transfer process.

Fig. 39.  (Color online) The schematic of Si-CMOS, high frequency GaAs HEMT, and high power GaN PA integrated on a single piece of wafer.

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Deleonibus S. Physical and technological limitations of nano CMOS devices to the end of the roadmap and beyond. Eur Phys J Appl Phys, 2006, 36, 197 doi: 10.1051/epjap:2006158
[2]
Ito T, Okazaki S. Pushing the limits of lithography. Nature, 2000, 406, 1027 doi: 10.1038/35023233
[3]
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[4]
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[5]
Passlack M, Zurcher P, Rajagopalan K, et al. High mobility III–V MOSFETs for RF and digital applications. 2007 IEEE Int Electron Devices Meet, 2007, 621
[6]
Kim R H, Kim D H, Xiao J L, et al. Waterproof AlInGaP optoelectronics on stretchable substrates with applications in biomedicine and robotics. Nat Mater, 2010, 9, 929 doi: 10.1038/nmat2879
[7]
Ko H, Takei K, Kapadia R, et al. Ultrathin compound semiconductor on insulator layers for high-performance nanoscale transistors. Nature, 2010, 468, 286 doi: 10.1038/nature09541
[8]
Yoon J, Jo S, Chun I S, et al. GaAs photovoltaics and optoelectronics using releasable multilayer epitaxial assemblies. Nature, 2010, 465, 329 doi: 10.1038/nature09054
[9]
Lin J J, You T G, Jin T T, et al. Wafer-scale heterogeneous integration InP on trenched Si with a bubble-free interface. APL Mater, 2020, 8, 051110 doi: 10.1063/5.0004427
[10]
Lin J J, You T G, Wang M, et al. Efficient ion-slicing of InP thin film for Si-based hetero-integration. Nanotechnology, 2018, 29, 504002 doi: 10.1088/1361-6528/aae281
[11]
Lee K H, Bao S, Fitzgerald E, et al. Integration of III–V materials and Si-CMOS through double layer transfer process. 2014 4th IEEE Int Work Low Temp Bond 3D Integr LTB-3D, 2014, 32
[12]
Lee K H, Bao S Y, Kohen D, et al. Monolithic integration of III–V HEMT and Si-CMOS through TSV-less 3D wafer stacking. 2015 IEEE 65th Electronic Components and Technology Conference (ECTC), 2015, 560
[13]
Lee K H, Bao S Y, Lee K E K, et al. Integration of 200 mm Si-CMOS and III–V materials through wafer bonding. 2017 5th International Workshop on Low Temperature Bonding for 3D Integration (LTB-3D), 2017, 30
[14]
Yan Y Q, Huang K, Zhou H Y, et al. Wafer-scale fabrication of 42° rotated Y-cut LiTaO3-on-insulator (LTOI) substrate for a SAW resonator. ACS Appl Electron Mater, 2019, 1, 1660 doi: 10.1021/acsaelm.9b00351
[15]
Huang K, Jia Q, You T G, et al. Investigation on thermodynamics of ion-slicing of GaN and heterogeneously integrating high-quality GaN films on CMOS compatible Si(100) substrates. Sci Rep, 2017, 7, 15017. doi: 10.1038/s41598-017-15094-1
[16]
Yi A L, Zheng Y, Huang H, et al. Wafer-scale 4H-silicon carbide-on-insulator (4H-SiCOI) platform for nonlinear integrated optical devices. Opt Mater, 2020, 107, 109990 doi: 10.1016/j.optmat.2020.109990
[17]
Lei D, Lee K H, Bao S Y, et al. GeSn-on-insulator substrate formed by direct wafer bonding. Appl Phys Lett, 2016, 109, 022106 doi: 10.1063/1.4958844
[18]
Xu W H, Wang Y, You T G, et al. First demonstration of waferscale heterogeneous integration of Ga2O3 MOSFETs on SiC and Si substrates by ion-cutting process. 2019 IEEE International Electron Devices Meeting (IEDM), 2019, 12.5. 1
[19]
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[20]
Tong Q Y, Gösele U. Semiconductor wafer bonding: Recent developments. Mater Chem Phys, 1994, 37, 101 doi: 10.1016/0254-0584(94)90080-9
[21]
Lasky J B, Stiffler S R, White F R, et al. Silicon-on-insulator (SOI) by bonding and ETCH-back. 1985 Int Electron Devices Meet, 1985, 684
[22]
Plößl A. Wafer direct bonding: Tailoring adhesion between brittle materials. Mater Sci Eng R, 1999, 25, 1 doi: 10.1016/S0927-796X(98)00017-5
[23]
Turner K T, Spearing S M. Modeling of direct wafer bonding: Effect of wafer bow and etch patterns. J Appl Phys, 2002, 92, 7658 doi: 10.1063/1.1521792
[24]
Taniyama S, Wang Y H, Fujino M, et al. Room temperature wafer bonding using surface activated bonding method. 2008 IEEE 9th VLSI Packag Work Jpn, 2008, 141
[25]
Takagi H, Kikuchi K, Maeda R, et al. Surface activated bonding of silicon wafers at room temperature. Appl Phys Lett, 1996, 68, 2222 doi: 10.1063/1.115865
[26]
Howlader M M R, Watanabe T, Suga T. Investigation of the bonding strength and interface current of p-Si/n-GaAs wafers bonded by surface activated bonding at room temperature. J Vac Sci Technol B, 2001, 19, 2114 doi: 10.1116/1.1414115
[27]
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    Received: 18 May 2020 Revised: 18 June 2020 Online: Accepted Manuscript: 04 September 2020Uncorrected proof: 11 September 2020Published: 08 February 2021

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      Shuyu Bao, Yue Wang, Khaw Lina, Li Zhang, Bing Wang, Wardhana Aji Sasangka, Kenneth Eng Kian Lee, Soo Jin Chua, Jurgen Michel, Eugene Fitzgerald, Chuan Seng Tan, Kwang Hong Lee. A review of silicon-based wafer bonding processes, an approach to realize the monolithic integration of Si-CMOS and III–V-on-Si wafers[J]. Journal of Semiconductors, 2021, 42(2): 023106. doi: 10.1088/1674-4926/42/2/023106 S Y Bao, Y Wang, K Lina, L Zhang, B Wang, W A Sasangka, K E K Lee, S J Chua, J Michel, E Fitzgerald, C S Tan, K H Lee, A review of silicon-based wafer bonding processes, an approach to realize the monolithic integration of Si-CMOS and III–V-on-Si wafers[J]. J. Semicond., 2021, 42(2): 023106. doi: 10.1088/1674-4926/42/2/023106.Export: BibTex EndNote
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      Shuyu Bao, Yue Wang, Khaw Lina, Li Zhang, Bing Wang, Wardhana Aji Sasangka, Kenneth Eng Kian Lee, Soo Jin Chua, Jurgen Michel, Eugene Fitzgerald, Chuan Seng Tan, Kwang Hong Lee. A review of silicon-based wafer bonding processes, an approach to realize the monolithic integration of Si-CMOS and III–V-on-Si wafers[J]. Journal of Semiconductors, 2021, 42(2): 023106. doi: 10.1088/1674-4926/42/2/023106

      S Y Bao, Y Wang, K Lina, L Zhang, B Wang, W A Sasangka, K E K Lee, S J Chua, J Michel, E Fitzgerald, C S Tan, K H Lee, A review of silicon-based wafer bonding processes, an approach to realize the monolithic integration of Si-CMOS and III–V-on-Si wafers[J]. J. Semicond., 2021, 42(2): 023106. doi: 10.1088/1674-4926/42/2/023106.
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      A review of silicon-based wafer bonding processes, an approach to realize the monolithic integration of Si-CMOS and III–V-on-Si wafers

      doi: 10.1088/1674-4926/42/2/023106
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      • Author Bio:

        Shuyu Bao received her B.Eng. (Hons.) degree in 2013 in Materials Engineering and Ph.D degree in 2018 in Electrical & Electronic Engineering from Nanyang Technological University (NTU), Singapore. Currently, she is a senior postdoctoral researcher in Singapore-MIT alliance for research and technology (SMART). Her research interests include low temperature wafer bonding and development of multi-color LED and CMOS-driven LED through heterogeneous material integration

        Yue Wang received her B.Eng. (Hons.) degree in 2010 and Ph.D degree in 2016 in Electrical & Computer Engineering from National University of Singapore. Currently, she is a research scientist in Singapore-MIT alliance for research and technology (SMART). Her research interest is the monolithic integration of III-V electronic and optoelectronic devices on silicon

        Khaw Lina received her B.Eng. (Hons.) degree in 2010 in Materials Engineering from Nanyang Technological University (NTU), Singapore. Her research interest is on wafer bonding for integrated LED and HEMT/Si CMOS platform

        Li Zhang received his B.Eng. (Hons.) and B.A. degrees in electrical engineering and economics from National University of Singapore in 2010 and Ph.D. degree from NUS graduate school for integrative science and engineering from National University of Singapore in 2016. His research interest is GaN-on-Si epitaxy and integrated GaN LED/Si CMOS platform

        Bing Wang is Assoc. Professor in the School of Electronics and Information Technology at the Sun Yat-Sen University, China. He received his B. S. degree in Electronic Science and Technology from Zhengzhou University, Zhengzhou, China, in 2005, M.S. degree in Optical Engineering from Huazhong University of Science and Technology, Wuhan, China, in 2007, and Ph.D. degree in Communication and Information Systems, from Peking University, Beijing, China, in 2012. His research interests cover optoelectronic devices, integrated photonics, and optical interconnect systems

        Wardhana Aji Sasangka received his Ph.D in advanced materials science for micro- and nano-system from Nanyang Technological University in 2012. He has broad research interests such as GaN reliability, nanowires growth, thin film interdiffusion, and crystal defect characterization. He is an active member of organizing committee in International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)

        Kenneth Eng Kian Lee is the Senior Scientific Director of the Low Energy Electronic Systems (LEES) center of the Singapore-MIT Alliance for Research and Technology (SMART). He drives the core program effort to create a hybrid III-V + CMOS integrated circuit platform based on foundry-standard CMOS process flows, to enable new integrated electronic and photonic systems. He had prior stints in Singapore’s Ministry of Defence, Temasek Laboratories at NTU, and DSO National Laboratories. He received his BS and MS degrees from UIUC in 1998 and 1999, respectively, and his PhD from MIT in 2009, all in Electrical Engineering

        Soo Jin Chua is a Professor in the Depart ment of Electrical Engineering, National University of Singapore, Principal Scientist in the Institute of Materials Research and Engineering (IMRE) and Principal Investigator in SMART. His research area is in Semiconductor Optoelectronics

        Jurgen Michel is a Senior Research Scientist in the Microphotonics Center and a Senior Lecturer in the Department of Materials Science and Engineering at the Massachusetts Institute of Technology.   He leads research projects in silicon-based photonic materials and devices as well as advanced solar cell designs.  His main focus is currently on on-chip WDM devices, Ge-based high performance detectors and modulators, and Ge-based lasers with the goal to implement active photonics devices in CMOS based chips

        Eugene Fitzgerald is the Merton C. Flemings SMA Professor of Materials Engineering at the Massachusetts Institute of Technology. He is Chief Executive Officer and Director of the Singapore–MIT alliance for research and technology (SMART), Singapore. He is also the Lead Principal Investigator (PI) of SMART Low Energy Electronic Systems (LEES) Interdisciplinary Research Group (IRG)

        Chuan Seng Tan is a Professor with the School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore. He received the Ph.D. degree in electrical engineering from Massachusetts Institute of Technology, Cambridge, in 2006. His research interests are semiconductor process technology and device physics. Currently he is working on process technology of three-dimensional integrated circuits (3-D ICs), as well as engineered substrate (Si/Ge/Sn) for group-IV photonics

        Kwang Hong Lee received the B.Eng. (Hons.) and Ph.D. degrees in materials science and engineering from Nanyang Technological University, Singapore, in 2006 and 2011, respectively. He was a Principal Research Scientist with the Singapore–MIT Alliance for Research and Technology, working on creating novel combinations of materials with silicon for use in monolithic processes

      • Corresponding author: shuyu@smart.mit.eduwangb266@mail.sysu.edu.cnleek0046@e.ntu.edu.sg
      • Received Date: 2020-05-18
      • Revised Date: 2020-06-18
      • Published Date: 2021-02-10

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