A novel 4H-SiC trench MOSFET with double shielding structures and ultralow gate-drain charge

Xiaorong Luo; Tian Liao; Jie Wei; Jian Fang; Fei Yang; Bo Zhang

doi:10.1088/1674-4926/40/5/052803

J. Semicond. > 2019, Volume 40 > Issue 5 > 052803, doi: 10.1088/1674-4926/40/5/052803

ARTICLES

A novel 4H-SiC trench MOSFET with double shielding structures and ultralow gate-drain charge

Xiaorong Luo^1,, Tian Liao¹, Jie Wei¹, Jian Fang¹, Fei Yang² and Bo Zhang¹

+ Author Affiliations

Corresponding author: Xiaorong Luo, Email: xrluo@uestc.edu.cn

Abstract: A new ultralow gate–drain charge (Q_GD) 4H-SiC trench MOSFET is presented and its mechanism is investigated by simulation. The novel MOSFET features double shielding structures (DS-MOS): one is the grounded split gate (SG), the other is the P⁺ shielding region (PSR). Both the SG and the PSR reduce the coupling effect between the gate and the drain, and transform the most part of the gate–drain capacitance (C_GD) into the gate–source capacitance (C_GS) and drain–source capacitance (C_DS) in series. Thus the C_GD is reduced and the proposed DS-MOS obtains ultralow Q_GD. Compared with the double-trench MOSFET (DT-MOS) and the conventional trench MOSFET (CT-MOS), the proposed DS-MOS decreases the Q_GD by 85% and 81%, respectively. Moreover, the figure of merit (FOM), defined as the product of specific on-resistance (R_{on, sp}) and Q_GD (R_{on, sp}Q_GD), is reduced by 84% and 81%, respectively.

Key words: SiC trench MOSFET, reverse transfer capacitance, gate-drain charge, figure of merit

References

[1]	Pittini R, Zhang Z, Andersen M A E. Switching performance evaluation of commercial SiC power devices (SiC JFET and SiC MOSFET) in relation to the gate driver complexity. IEEE ECCE Asia Downunder, 2013, 233
[2]	Zhang X, Yao C, Li C, et al. A wide bandgap device-based isolated quasi-switched-capacitor DC/DC converter. IEEE Trans Power Electron, 2014, 29(5), 2500 doi: 10.1109/TPEL.2013.2287501
[3]	Abbatelli L, Macauda M, Catalisano G, et al. Cost benefits on high frequency converter system based on SiC MOSFET approach. PCIM Europe; International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management, 2014, 1
[4]	T Kimoto, J A Cooper. Fundamentals of silicon carbide technology: growth, characterization, devices, and applications. Singapore: Wiley, 2014
[5]	Tega N, Hisamoto D, Shima A, et al. Channel properties of SiC trench-etched double-implanted MOS (TED MOS). IEEE Trans Electron Devices, 2016, 63(9), 1 doi: 10.1109/ted.2016.2587799
[6]	Zhang Q, Gomez M. 1600V 4H-SiC UMOSFETs with dual buffer layers. International Symposium on Power Semiconductor Devices and ICs, 2005, 211
[7]	Sui Y, Tsuji T, Cooper J A. On-state characteristics of SiC power UMOSFETs on 115-μm drift layers. IEEE Electron Device Lett, 2005, 26(4), 255 doi: 10.1109/LED.2005.845495
[8]	Tega N, Yoshimoto H,Hisamoto D, et al. Novel trench-etched double-diffused SiC MOS (TED MOS) for overcoming tradeoff between R_onA and Q_gd. International Symposium on Power Semiconductor Devices and ICs, 2015, 81
[9]	Cooper J A, Melloch M R, Singh R, et al. Status and prospects for SiC power MOSFETs. IEEE Trans Electron Devices, 2002, 49(4), 658 doi: 10.1109/16.992876
[10]	Hiroshi Y, Hatayama N H. Increased channel mobility in 4H-SiC UMOSFETs using on-axis substrates. Mater Sci Forum, 2007, 556/557, 807 doi: 10.4028/www.scientific.net/MSF.556-557
[11]	Tan J, Cooper J A, Melloch M R. High-voltage accumulation-layer UMOSFET’s in 4H-SiC. IEEE Electron Device Lett, 1998, 19(12), 487 doi: 10.1109/55.735755
[12]	Kagawa Y, Fujiwara N, Sugawara K, et al. 4H-SiC trench MOSFET with bottom oxide protection. Mater Sci Forum, 2014, 778–780, 907 doi: 10.4028/www.scientific.net/MSF.778-780
[13]	Wang Y, Ma Y C, Hao Y, et al. Simulation study of 4H-SiC UMOSFET structure with p⁺-polySi/SiC shielded region. IEEE Trans Electron Devices, 2017, 64(9) doi: 10.1109/TED.2017.2723502
[14]	Wei J, Zhang M, Jiang H, et al. Charge storage effect in SiC trench MOSFET with a floating p-shield and its impact on dynamic performances. International Symposium on Power Semiconductor Devices and ICs, 2017, 387
[15]	Khan I A, Cooper J A, Capano M A, et al. High-voltage UMOSFETs in 4H SiC. International Symposium on Power Semiconductor Devices and ICs, 2002, 157
[16]	Wei J, Zhang M, Jiang H P, et al. Dynamic degradation in SiC trench MOSFET with a floating p-shield revealed with numerical simulations. IEEE Trans Electron Devices, 2017, 64(4), 2592 doi: 10.1109/TED.2017.2697763
[17]	Nakamura T, Nakano Y, Aketa M, et al. Performance SiC trench devices with ultra-low R_on. Electron Devices Meeting, 2011, 26.5.1
[18]	Goarin P, Koops G E J, Dalen R V, et al. Split-gate resurf stepped oxide (RSO) MOSFETs for 25 V applications with record low gate-to-drain charge. International Symposium on Power Semiconductor Devices and ICs, 2007, 61
[19]	Luo X, Ma D, Tan Q, et al. A split gate power FINFET with improved ON-resistance and switching performance. IEEE Electron Device Lett, 2016, 37(9), 1185 doi: 10.1109/LED.2016.2591780
[20]	Zhou X, Yue R, Zhang J, et al. 4H-SiC trench MOSFET with floating/grounded junction barrier-controlled gate structure. IEEE Trans Electron Devices, 2017, 64(11), 4568 doi: 10.1109/TED.2017.2755721
[21]	J Lutz, U Scheuermann, H Schlangenotto, et al. Semiconductor power devices: physics, characteristics, reliability. New York: Spring-Verlag, 2011

Fig. 1. (Color online) Schematic cross section of the (a) proposed DS-MOS, (b) DT-MOS, and (c) CT-MOS.

DownLoad: Full-Size Img PowerPoint

Fig. 2. (Color online) Capacitance distribution for (a) trench gate MOSFET without SG & PSR, (b) split trench gate MOSFET with SG, (c) DT-MOS, and (d) DS-MOS.

DownLoad: Full-Size Img PowerPoint

Fig. 3. (Color online) C_GD of the four structures in Fig. 2.

DownLoad: Full-Size Img PowerPoint

Fig. 4. (Color online) Tradeoff between R_{on, sp} (@V_GS = 20 V, V_DS = 1 V) and BV(@V_GS = 0 V) for the DS-MOS (a) with varied L_ox as the function of L_s, T_ox is set as 0.2 μm and (b) with varied T_ox as the function of L_s, L_ox is set as 0.3 μm. OBD means oxide breakdown and ABD means avalanche breakdown. Optimized R_{on, sp} = 4.08 mΩ·cm² (denoted as “A”) and BV_R = 1435 V (denoted as “B”). (c) Influence of T_ox, L_ox, and L_s on FOM. (d) On-state depletion boundary (@V_GS = 20 V, V_DS = 1 V) and electron density with varied T_ox and L_ox at L_s = 1.1 μm. The white lines are the depletion boundaries.

DownLoad: Full-Size Img PowerPoint

Fig. 5. (Color online) Dependence of C_GD (@V_DS = 600 V) on L_s, T_ox and L_ox for DS-MOS.

DownLoad: Full-Size Img PowerPoint

Fig. 6. (Color online) On-state output characteristic curves of the three devices at V_GS = 20 V.

DownLoad: Full-Size Img PowerPoint

Fig. 7. (Color online) Comparison of (a) C_GD and (b) Q_GD of the DS-MOS, DT-MOS and CT-MOS. The extracted Q_GD is 26, 174 and 138 nC/cm², respectively. The inset is the simulation circuit.

DownLoad: Full-Size Img PowerPoint

Fig. 8. (Color online) Tradeoff between R_{on, sp} (V_GS = 20 V, V_DS = 1 V) and Q_GD.

DownLoad: Full-Size Img PowerPoint

Fig. 9. (Color online) (a) Turn-off waveforms of the DS-MOS, DT-MOS and CT-MOS, respectively. (b) Simulation circuit of the turn-off characteristics.

DownLoad: Full-Size Img PowerPoint

Fig. 10. (Color online) (a) Dependence of E_on + E_off on R_G (V_DS = 600 V, V_GS = 0/20 V, I_load = 100 A/cm²). (b) Comparison of power losses as a function of switching frequency f (R_G = 20 Ω).

DownLoad: Full-Size Img PowerPoint

Fig. 11. (a) 3-D view of DS-MOS. (b) Schematic cross section along the cut line AA’.

DownLoad: Full-Size Img PowerPoint

Table 1. Simulation parameters of the proposed structure and contrastive structures.

Symbol	Description	Value (μm)
D_p	Vertical implantation depth of the PSR	1.5
W_p	Later implantation width of the PSR	0.2
D_t	Depth of the trench	1.5
T_SG	Thickness of split gate	0.2
W	Width of half cell	3.5
W_t	Width of half trench	0.5

DownLoad: CSV

Table 2. Performance comparison of the three MOSFETs.

Parameter	DS-MOS	DT-MOS	CT-MOS
dV/dt (kV/μs)	16.1	4.7	5.5
dI/dt (kA/μs)	2.6	2.2	1.6
Q_GD (nC/cm²)	26	174	138
C_GD (pF/cm²) (@V_DS = 600 V)	13	68	83
R_{on, sp} (mΩ·cm²)	4.08	3.72	3.96
R_{on, sp}Q_GD (mΩ·nC)	106	647	546
V_BR (V)	1435	1460	1233

DownLoad: CSV

[1]	Pittini R, Zhang Z, Andersen M A E. Switching performance evaluation of commercial SiC power devices (SiC JFET and SiC MOSFET) in relation to the gate driver complexity. IEEE ECCE Asia Downunder, 2013, 233
[2]	Zhang X, Yao C, Li C, et al. A wide bandgap device-based isolated quasi-switched-capacitor DC/DC converter. IEEE Trans Power Electron, 2014, 29(5), 2500 doi: 10.1109/TPEL.2013.2287501
[3]	Abbatelli L, Macauda M, Catalisano G, et al. Cost benefits on high frequency converter system based on SiC MOSFET approach. PCIM Europe; International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management, 2014, 1
[4]	T Kimoto, J A Cooper. Fundamentals of silicon carbide technology: growth, characterization, devices, and applications. Singapore: Wiley, 2014
[5]	Tega N, Hisamoto D, Shima A, et al. Channel properties of SiC trench-etched double-implanted MOS (TED MOS). IEEE Trans Electron Devices, 2016, 63(9), 1 doi: 10.1109/ted.2016.2587799
[6]	Zhang Q, Gomez M. 1600V 4H-SiC UMOSFETs with dual buffer layers. International Symposium on Power Semiconductor Devices and ICs, 2005, 211
[7]	Sui Y, Tsuji T, Cooper J A. On-state characteristics of SiC power UMOSFETs on 115-μm drift layers. IEEE Electron Device Lett, 2005, 26(4), 255 doi: 10.1109/LED.2005.845495
[8]	Tega N, Yoshimoto H,Hisamoto D, et al. Novel trench-etched double-diffused SiC MOS (TED MOS) for overcoming tradeoff between R_onA and Q_gd. International Symposium on Power Semiconductor Devices and ICs, 2015, 81
[9]	Cooper J A, Melloch M R, Singh R, et al. Status and prospects for SiC power MOSFETs. IEEE Trans Electron Devices, 2002, 49(4), 658 doi: 10.1109/16.992876
[10]	Hiroshi Y, Hatayama N H. Increased channel mobility in 4H-SiC UMOSFETs using on-axis substrates. Mater Sci Forum, 2007, 556/557, 807 doi: 10.4028/www.scientific.net/MSF.556-557
[11]	Tan J, Cooper J A, Melloch M R. High-voltage accumulation-layer UMOSFET’s in 4H-SiC. IEEE Electron Device Lett, 1998, 19(12), 487 doi: 10.1109/55.735755
[12]	Kagawa Y, Fujiwara N, Sugawara K, et al. 4H-SiC trench MOSFET with bottom oxide protection. Mater Sci Forum, 2014, 778–780, 907 doi: 10.4028/www.scientific.net/MSF.778-780
[13]	Wang Y, Ma Y C, Hao Y, et al. Simulation study of 4H-SiC UMOSFET structure with p⁺-polySi/SiC shielded region. IEEE Trans Electron Devices, 2017, 64(9) doi: 10.1109/TED.2017.2723502
[14]	Wei J, Zhang M, Jiang H, et al. Charge storage effect in SiC trench MOSFET with a floating p-shield and its impact on dynamic performances. International Symposium on Power Semiconductor Devices and ICs, 2017, 387
[15]	Khan I A, Cooper J A, Capano M A, et al. High-voltage UMOSFETs in 4H SiC. International Symposium on Power Semiconductor Devices and ICs, 2002, 157
[16]	Wei J, Zhang M, Jiang H P, et al. Dynamic degradation in SiC trench MOSFET with a floating p-shield revealed with numerical simulations. IEEE Trans Electron Devices, 2017, 64(4), 2592 doi: 10.1109/TED.2017.2697763
[17]	Nakamura T, Nakano Y, Aketa M, et al. Performance SiC trench devices with ultra-low R_on. Electron Devices Meeting, 2011, 26.5.1
[18]	Goarin P, Koops G E J, Dalen R V, et al. Split-gate resurf stepped oxide (RSO) MOSFETs for 25 V applications with record low gate-to-drain charge. International Symposium on Power Semiconductor Devices and ICs, 2007, 61
[19]	Luo X, Ma D, Tan Q, et al. A split gate power FINFET with improved ON-resistance and switching performance. IEEE Electron Device Lett, 2016, 37(9), 1185 doi: 10.1109/LED.2016.2591780
[20]	Zhou X, Yue R, Zhang J, et al. 4H-SiC trench MOSFET with floating/grounded junction barrier-controlled gate structure. IEEE Trans Electron Devices, 2017, 64(11), 4568 doi: 10.1109/TED.2017.2755721
[21]	J Lutz, U Scheuermann, H Schlangenotto, et al. Semiconductor power devices: physics, characteristics, reliability. New York: Spring-Verlag, 2011

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Received: 07 January 2019 Revised: 25 March 2019 Online: Accepted Manuscript: 20 April 2019Uncorrected proof: 24 April 2019Published: 08 May 2019

Article Navigation > Journal of Semiconductors > 2019 > 40(5): 052803

Xiaorong Luo, Tian Liao, Jie Wei, Jian Fang, Fei Yang, Bo Zhang. A novel 4H-SiC trench MOSFET with double shielding structures and ultralow gate-drain charge[J]. Journal of Semiconductors, 2019, 40(5): 052803. doi: 10.1088/1674-4926/40/5/052803 X R Luo, T Liao, J Wei, J Fang, F Yang, B Zhang, A novel 4H-SiC trench MOSFET with double shielding structures and ultralow gate-drain charge[J]. J. Semicond., 2019, 40(5): 052803. doi: 10.1088/1674-4926/40/5/052803.Export: BibTex EndNote

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Xiaorong Luo, Tian Liao, Jie Wei, Jian Fang, Fei Yang, Bo Zhang. A novel 4H-SiC trench MOSFET with double shielding structures and ultralow gate-drain charge[J]. Journal of Semiconductors, 2019, 40(5): 052803. doi: 10.1088/1674-4926/40/5/052803

X R Luo, T Liao, J Wei, J Fang, F Yang, B Zhang, A novel 4H-SiC trench MOSFET with double shielding structures and ultralow gate-drain charge[J]. J. Semicond., 2019, 40(5): 052803. doi: 10.1088/1674-4926/40/5/052803.

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A novel 4H-SiC trench MOSFET with double shielding structures and ultralow gate-drain charge

doi: 10.1088/1674-4926/40/5/052803

1.
State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China
2.
Global Energy Interconnection Research Institute, Beijing 102209, China

More Information

Corresponding author: Email: xrluo@uestc.edu.cn
Received Date: 2019-01-07
Revised Date: 2019-03-25
Published Date: 2019-05-01

Abstract

Abstract

A new ultralow gate–drain charge (Q_GD) 4H-SiC trench MOSFET is presented and its mechanism is investigated by simulation. The novel MOSFET features double shielding structures (DS-MOS): one is the grounded split gate (SG), the other is the P⁺ shielding region (PSR). Both the SG and the PSR reduce the coupling effect between the gate and the drain, and transform the most part of the gate–drain capacitance (C_GD) into the gate–source capacitance (C_GS) and drain–source capacitance (C_DS) in series. Thus the C_GD is reduced and the proposed DS-MOS obtains ultralow Q_GD. Compared with the double-trench MOSFET (DT-MOS) and the conventional trench MOSFET (CT-MOS), the proposed DS-MOS decreases the Q_GD by 85% and 81%, respectively. Moreover, the figure of merit (FOM), defined as the product of specific on-resistance (R_{on, sp}) and Q_GD (R_{on, sp}Q_GD), is reduced by 84% and 81%, respectively.
- SiC trench MOSFET,
- reverse transfer capacitance,
- gate-drain charge,
- figure of merit

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References(21)

References

[1]	Pittini R, Zhang Z, Andersen M A E. Switching performance evaluation of commercial SiC power devices (SiC JFET and SiC MOSFET) in relation to the gate driver complexity. IEEE ECCE Asia Downunder, 2013, 233
[2]	Zhang X, Yao C, Li C, et al. A wide bandgap device-based isolated quasi-switched-capacitor DC/DC converter. IEEE Trans Power Electron, 2014, 29(5), 2500 doi: 10.1109/TPEL.2013.2287501
[3]	Abbatelli L, Macauda M, Catalisano G, et al. Cost benefits on high frequency converter system based on SiC MOSFET approach. PCIM Europe; International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management, 2014, 1
[4]	T Kimoto, J A Cooper. Fundamentals of silicon carbide technology: growth, characterization, devices, and applications. Singapore: Wiley, 2014
[5]	Tega N, Hisamoto D, Shima A, et al. Channel properties of SiC trench-etched double-implanted MOS (TED MOS). IEEE Trans Electron Devices, 2016, 63(9), 1 doi: 10.1109/ted.2016.2587799
[6]	Zhang Q, Gomez M. 1600V 4H-SiC UMOSFETs with dual buffer layers. International Symposium on Power Semiconductor Devices and ICs, 2005, 211
[7]	Sui Y, Tsuji T, Cooper J A. On-state characteristics of SiC power UMOSFETs on 115-μm drift layers. IEEE Electron Device Lett, 2005, 26(4), 255 doi: 10.1109/LED.2005.845495
[8]	Tega N, Yoshimoto H,Hisamoto D, et al. Novel trench-etched double-diffused SiC MOS (TED MOS) for overcoming tradeoff between R_onA and Q_gd. International Symposium on Power Semiconductor Devices and ICs, 2015, 81
[9]	Cooper J A, Melloch M R, Singh R, et al. Status and prospects for SiC power MOSFETs. IEEE Trans Electron Devices, 2002, 49(4), 658 doi: 10.1109/16.992876
[10]	Hiroshi Y, Hatayama N H. Increased channel mobility in 4H-SiC UMOSFETs using on-axis substrates. Mater Sci Forum, 2007, 556/557, 807 doi: 10.4028/www.scientific.net/MSF.556-557
[11]	Tan J, Cooper J A, Melloch M R. High-voltage accumulation-layer UMOSFET’s in 4H-SiC. IEEE Electron Device Lett, 1998, 19(12), 487 doi: 10.1109/55.735755
[12]	Kagawa Y, Fujiwara N, Sugawara K, et al. 4H-SiC trench MOSFET with bottom oxide protection. Mater Sci Forum, 2014, 778–780, 907 doi: 10.4028/www.scientific.net/MSF.778-780
[13]	Wang Y, Ma Y C, Hao Y, et al. Simulation study of 4H-SiC UMOSFET structure with p⁺-polySi/SiC shielded region. IEEE Trans Electron Devices, 2017, 64(9) doi: 10.1109/TED.2017.2723502
[14]	Wei J, Zhang M, Jiang H, et al. Charge storage effect in SiC trench MOSFET with a floating p-shield and its impact on dynamic performances. International Symposium on Power Semiconductor Devices and ICs, 2017, 387
[15]	Khan I A, Cooper J A, Capano M A, et al. High-voltage UMOSFETs in 4H SiC. International Symposium on Power Semiconductor Devices and ICs, 2002, 157
[16]	Wei J, Zhang M, Jiang H P, et al. Dynamic degradation in SiC trench MOSFET with a floating p-shield revealed with numerical simulations. IEEE Trans Electron Devices, 2017, 64(4), 2592 doi: 10.1109/TED.2017.2697763
[17]	Nakamura T, Nakano Y, Aketa M, et al. Performance SiC trench devices with ultra-low R_on. Electron Devices Meeting, 2011, 26.5.1
[18]	Goarin P, Koops G E J, Dalen R V, et al. Split-gate resurf stepped oxide (RSO) MOSFETs for 25 V applications with record low gate-to-drain charge. International Symposium on Power Semiconductor Devices and ICs, 2007, 61
[19]	Luo X, Ma D, Tan Q, et al. A split gate power FINFET with improved ON-resistance and switching performance. IEEE Electron Device Lett, 2016, 37(9), 1185 doi: 10.1109/LED.2016.2591780
[20]	Zhou X, Yue R, Zhang J, et al. 4H-SiC trench MOSFET with floating/grounded junction barrier-controlled gate structure. IEEE Trans Electron Devices, 2017, 64(11), 4568 doi: 10.1109/TED.2017.2755721
[21]	J Lutz, U Scheuermann, H Schlangenotto, et al. Semiconductor power devices: physics, characteristics, reliability. New York: Spring-Verlag, 2011

A novel 4H-SiC trench MOSFET with double shielding structures and ultralow gate-drain charge

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