Towards secure computation and trusted silicon: emerging trends in ISSCC 2026 hardware security

Wenping Zhu; Hanning Wang; Bohan Yang; Leibo Liu

doi:10.1088/1674-4926/26040035

J. Semicond. > 2026, Volume 47 > Issue 7 > 070201

RESEARCH HIGHLIGHTS

Towards secure computation and trusted silicon: emerging trends in ISSCC 2026 hardware security

Wenping Zhu^{1, 2, 3}, Hanning Wang^{1, 2, 3}, Bohan Yang^{1, 2, 3} and Leibo Liu^{1, 2, 3,}

+ Author Affiliations

1. School of Integrated Circuits, Tsinghua University, Beijing 100084, China
2. State Key Laboratory of Cryptography and Digital Economy Security, Tsinghua University, Beijing 100084, China
3. Beijing National Research Center for Information Science and Technology (BNRist), Tsinghua University, Beijing 100084, China

Author Bio:

Wenping Zhu received the B.S. degree from the School of Microelectronics, Xidian University, Xi’an, China, in 2008, and the Ph.D. degree from the Institute of Microelectronics, Tsinghua University, Beijing, China, in 2016. He is currently a Senior Engineer with the School of Integrated Circuits, Tsinghua University. His main research interests include mobile computing and VLSI SoC design, and cryptographic accelerators.

Hanning Wang received the B.S. degree in network engineering and the M.S. degree in computer science and technology from China University of Geosciences, Wuhan, China, in 2009 and 2012, respectively. He is currently an Engineer with the School of Integrated Circuits, Tsinghua University, Beijing, China. His current research interests include hardware security and cryptographic engineering.

Bohan Yang received the B.S. degree from Xi’an Jiaotong University, Xi’an, China, in 2003, the joint M.S. degree from Tsinghua University, Beijing, China, and KU Leuven, Leuven, Belgium, in 2012, and the Ph.D. degree in EE from KU Leuven in 2018. From 2018 to 2024, he was a Post-Doctoral Researcher with Tsinghua University, where he has been an Assistant Researcher with the School of Integrated Circuits since 2024. His research interests include cryptographic chips, embedded security, true random number generators (TRNGs), and physical unclonable functions (PUFs).

Leibo Liu received the B.S. degree in electronic engineering from Tsinghua University, Beijing, China, in 1999, and the Ph.D. degree from the Institute of Microelectronics, Tsinghua University in 2004. He is currently a Professor with the School of Integrated Circuits, Tsinghua University. His current research interests include reconfigurable computing, cryptographic processors, hardware security, and very large-scale integration digital signal processing.

Corresponding author: Leibo Liu, liulb@tsinghua.edu.cn

DOI: 10.1088/1674-4926/26040035CSTR: 32376.14.1674-4926.26040035

References

[1]	Banerjee U, Juvekar C, Lee Y K, et al. Writing a good security paper for ISSCC (2025). arXiv, 2025
[2]	Mirabbasi S, Fujino L C. Through the looking glass: The 2025 edition: Trends in solid-state circuits from ISSCC. IEEE Solid State Circuits Mag, 2025, 17(1): 97 doi: 10.1109/MSSC.2024.3505093
[3]	Ramapragada K S T, Banerjee U. A 0.05mm² 1.19-to-7.34mW SQIsign-1D isogeny-based post-quantum signature verification accelerator for IoT. 2026 IEEE International Solid-State Circuits Conference (ISSCC), 2026: 432 doi: 10.1109/ISSCC49663.2026.11408981
[4]	Ghosh A, Li M C, Ding L K, et al. A 16nm 0.042mm² 0.66μJ/Ops lightweight mlwe pqc kem with cryptanalysis-asic co-optimization. 2026 IEEE International Solid-State Circuits Conference (ISSCC), 2026: 428 doi: 10.1109/ISSCC49663.2026.11409037
[5]	Yu X L, Sun Y, Zhao Y F, et al. A 28nm 0.48mJ/boot torus FHE processor for arbitrary computation on encrypted data. 2026 IEEE International Solid-State Circuits Conference (ISSCC), 2026: 426 doi: 10.1109/ISSCC49663.2026.11409039
[6]	Golder A, Kumar R, Taneja S, et al. HERACLES: 8192-way SIMD programmable scalable fully-homomorphic encryption SoC for privacy-preserving cloud computing in intel 3 CMOS. 2026 IEEE International Solid-State Circuits Conference (ISSCC), 2026: 424 doi: 10.1109/ISSCC49663.2026.11409291
[7]	Putra A, Cho H, Yune S, et al. OmniCrypt: A 435.86M-GOPS/W bootstrappable multi-scheme FHE accelerator with on-chip data generation for privacy-preserving computation. 2026 IEEE International Solid-State Circuits Conference (ISSCC), 2026: 430 doi: 10.1109/ISSCC49663.2026.11409291
[8]	Zhao C K, Shui H Y, Yang B H, et al. A 17%/27% area-/energy-overhead glitch-transition secure SHA-3 engine fusing dual-rail precharge logic and asymmetric masking. 2026 IEEE International Solid-State Circuits Conference (ISSCC), 2026: 434 doi: 10.1109/ISSCC49663.2026.11409007
[9]	Li M, Wan R T, Mathew S K, et al. TinyPAD: A 166μm²/lane variation-tolerant probing-attack detector for an 8Gb/s/lane chip-to-chip interface in 16nm FinFET. 2026 IEEE International Solid-State Circuits Conference (ISSCC), 2026: 436 doi: 10.1109/ISSCC49663.2026.11409005
[10]	Xu S F, Liu K Y, Chan L, et al. A sub-threshold all-NMOS reconfigurable PUF with secure configuration selection for stable 6b/cell. 2026 IEEE International Solid-State Circuits Conference (ISSCC), 2026: 438 doi: 10.1109/ISSCC49663.2026.11409111
[11]	Cheng K, Huang Y B, Yang Z S, et al. A 65nm 0.066pJ/b floating-latch-based true random number generator resilient to power-noise injection attacks. 2026 IEEE International Solid-State Circuits Conference (ISSCC), 2026: 442 doi: 10.1109/ISSCC49663.2026.11409134
[12]	Youn Y, Lim Y, Lee J, et al. A PVT variation- and attack-tolerant metastability-based TRNG using binary search in 2nm. 2026 IEEE International Solid-State Circuits Conference (ISSCC), 2026: 440 doi: 10.1109/ISSCC49663.2026.11409323
[13]	Zhu Y H, Zhu W P, Zhu M, et al. A 28nm 48KOPS 3.4µJ/op agile crypto-processor for post-quantum cryptography on multi-mathematical problems. 2022 IEEE International Solid-State Circuits Conference (ISSCC), 2022: 514 doi: 10.1109/ISSCC42614.2022.9731783
[14]	Zhu Y H, Zhu W P, Ouyang Y, et al. A 28nm 69.4kOPS 4.4μJ/op versatile post-quantum crypto-processor across multiple mathematical problems. 2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024: 298 doi: 10.1109/ISSCC49657.2024.10454332
[15]	Lu J H, Liu D S, Zhang J M, et al. A 28nm 84.9KOPS 1.82µJ/op RISC-V crypto-SoC with primitive-based deep-coupling unified post-quantum engine. 2025 Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2025: 1 doi: 10.23919/VLSITechnologyandCir65189.2025.11075179
[16]	Banerjee U, Pathak A, Chandrakasan A P. An energy-efficient configurable lattice cryptography processor for the quantum-secure Internet of Things. 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 2019: 46 doi: 10.1109/ISSCC.2019.8662528
[17]	Ghosh A, Mera J M B, Karmakar A, et al. A 334uW 0.158mm² saber learning with rounding based post-quantum crypto accelerator. 2022 IEEE Custom Integrated Circuits Conference (CICC), 2022: 1 doi: 10.1109/CICC53496.2022.9772859
[18]	Kim B, Park J, Moon S, et al. Configurable energy-efficient lattice-based post-quantum cryptography processor for IoT devices. ESSCIRC 2022-IEEE 48th European Solid State Circuits Conference (ESSCIRC). 2022: 525 doi: 10.1109/ESSCIRC55480.2022.9911531
[19]	Li A B, Lu J H, Liu D S, et al. A 273μW 0.34mm² efficient CRYSTALS-KYBER processor for PQC towards edge computing. 2024 IEEE European Solid-State Electronics Research Conference (ESSERC), 2024: 472 doi: 10.1109/ESSCIRC55480.2022.9911531
[20]	Lee H, Kwon H, Lee Y. A 2.7-to-13.3μJ/boot/slot flexible RNS-CKKS processor in 28nm CMOS technology for FHE-based privacy-preserving computing. 2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024: 296 doi: 10.1109/ISSCC49657.2024.10454420
[21]	Lu S J, Zhu W P, Yang B H, et al. A 28nm 4.05µJ/encryption 8.72kHMul/s reconfigurable multi-scheme fully homomorphic encryption processor for encrypted client-server computing. 2025 IEEE International Solid-State Circuits Conference (ISSCC), 2025: 1 doi: 10.1109/ISSCC49661.2025.10904812
[22]	Shi G M, Tan Z H, Cao D P, et al. A 28nm 68MOPS 0.18µJ/Op paillier homomorphic encryption processor with bit-serial sparse ciphertext computing. 2023 IEEE International Solid-State Circuits Conference (ISSCC), 2023: 242 doi: 10.1109/ISSCC42615.2023.10067522
[23]	Lin L H, Yang Y K, Yang C H. A 30.4GOPS/mW MK-CKKS processor for secure multi-party computation. 2025 IEEE International Solid-State Circuits Conference (ISSCC). 2025: 296 doi: 10.1109/ISSCC49661.2025.10904776
[24]	Zhang R L, Wang X Y, Liu K Y, et al. A 0.186-pJ per bit latch-based true random number generator featuring mismatch compensation and random noise enhancement. IEEE J Solid State Circuits, 2022, 57(8): 2498 doi: 10.1109/JSSC.2021.3137312
[25]	Lee J, Lee J, Youn Y, et al. A 1.7 pJ/bit 10 MHz calibration-free PVT variation and mismatch tolerant latch-based true random number generator in 4 nm FinFET. 2025 Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2025: 1 doi: 10.23919/VLSITechnologyandCir65189.2025.11075211
[26]	Kim J, Chae H. A 10-Gb/s true random number generator using ML-resistant middle square method. IEEE J Solid State Circuits, 2024, 59(7): 2321 doi: 10.1109/JSSC.2023.3346428
[27]	Hao J C, Zhuang Q S, Zhang J H, et al. A 98fJ/bit current-starved-ring-oscillator-based TRNG with high PVT tolerance and resilience to frequency injection attack up to 1V. 2024 IEEE Custom Integrated Circuits Conference (CICC), 2024: 1 doi: 10.1109/CICC60959.2024.10528979

Fig. 1. (Color online) Recent trends in cryptographic accelerators reported in ISSCC and related conferences. The figure highlights the bifurcation of hardware cryptography research into PQC-oriented and FHE-oriented accelerators, and emphasizes the increasing roles of programmability, algorithm–architecture co-design, and memory-system optimization.

DownLoad: Full-Size Img PowerPoint

Fig. 2. (Color online) Recent TRNG design trends in energy per bit and throughput. Beyond conventional efficiency metrics, recent ISSCC designs also emphasize robustness-oriented properties such as resilience to noise-injection attacks, elimination of warm-up latency, and tolerance to environmental and PVT variations.

DownLoad: Full-Size Img PowerPoint

[1]	Banerjee U, Juvekar C, Lee Y K, et al. Writing a good security paper for ISSCC (2025). arXiv, 2025
[2]	Mirabbasi S, Fujino L C. Through the looking glass: The 2025 edition: Trends in solid-state circuits from ISSCC. IEEE Solid State Circuits Mag, 2025, 17(1): 97 doi: 10.1109/MSSC.2024.3505093
[3]	Ramapragada K S T, Banerjee U. A 0.05mm² 1.19-to-7.34mW SQIsign-1D isogeny-based post-quantum signature verification accelerator for IoT. 2026 IEEE International Solid-State Circuits Conference (ISSCC), 2026: 432 doi: 10.1109/ISSCC49663.2026.11408981
[4]	Ghosh A, Li M C, Ding L K, et al. A 16nm 0.042mm² 0.66μJ/Ops lightweight mlwe pqc kem with cryptanalysis-asic co-optimization. 2026 IEEE International Solid-State Circuits Conference (ISSCC), 2026: 428 doi: 10.1109/ISSCC49663.2026.11409037
[5]	Yu X L, Sun Y, Zhao Y F, et al. A 28nm 0.48mJ/boot torus FHE processor for arbitrary computation on encrypted data. 2026 IEEE International Solid-State Circuits Conference (ISSCC), 2026: 426 doi: 10.1109/ISSCC49663.2026.11409039
[6]	Golder A, Kumar R, Taneja S, et al. HERACLES: 8192-way SIMD programmable scalable fully-homomorphic encryption SoC for privacy-preserving cloud computing in intel 3 CMOS. 2026 IEEE International Solid-State Circuits Conference (ISSCC), 2026: 424 doi: 10.1109/ISSCC49663.2026.11409291
[7]	Putra A, Cho H, Yune S, et al. OmniCrypt: A 435.86M-GOPS/W bootstrappable multi-scheme FHE accelerator with on-chip data generation for privacy-preserving computation. 2026 IEEE International Solid-State Circuits Conference (ISSCC), 2026: 430 doi: 10.1109/ISSCC49663.2026.11409291
[8]	Zhao C K, Shui H Y, Yang B H, et al. A 17%/27% area-/energy-overhead glitch-transition secure SHA-3 engine fusing dual-rail precharge logic and asymmetric masking. 2026 IEEE International Solid-State Circuits Conference (ISSCC), 2026: 434 doi: 10.1109/ISSCC49663.2026.11409007
[9]	Li M, Wan R T, Mathew S K, et al. TinyPAD: A 166μm²/lane variation-tolerant probing-attack detector for an 8Gb/s/lane chip-to-chip interface in 16nm FinFET. 2026 IEEE International Solid-State Circuits Conference (ISSCC), 2026: 436 doi: 10.1109/ISSCC49663.2026.11409005
[10]	Xu S F, Liu K Y, Chan L, et al. A sub-threshold all-NMOS reconfigurable PUF with secure configuration selection for stable 6b/cell. 2026 IEEE International Solid-State Circuits Conference (ISSCC), 2026: 438 doi: 10.1109/ISSCC49663.2026.11409111
[11]	Cheng K, Huang Y B, Yang Z S, et al. A 65nm 0.066pJ/b floating-latch-based true random number generator resilient to power-noise injection attacks. 2026 IEEE International Solid-State Circuits Conference (ISSCC), 2026: 442 doi: 10.1109/ISSCC49663.2026.11409134
[12]	Youn Y, Lim Y, Lee J, et al. A PVT variation- and attack-tolerant metastability-based TRNG using binary search in 2nm. 2026 IEEE International Solid-State Circuits Conference (ISSCC), 2026: 440 doi: 10.1109/ISSCC49663.2026.11409323
[13]	Zhu Y H, Zhu W P, Zhu M, et al. A 28nm 48KOPS 3.4µJ/op agile crypto-processor for post-quantum cryptography on multi-mathematical problems. 2022 IEEE International Solid-State Circuits Conference (ISSCC), 2022: 514 doi: 10.1109/ISSCC42614.2022.9731783
[14]	Zhu Y H, Zhu W P, Ouyang Y, et al. A 28nm 69.4kOPS 4.4μJ/op versatile post-quantum crypto-processor across multiple mathematical problems. 2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024: 298 doi: 10.1109/ISSCC49657.2024.10454332
[15]	Lu J H, Liu D S, Zhang J M, et al. A 28nm 84.9KOPS 1.82µJ/op RISC-V crypto-SoC with primitive-based deep-coupling unified post-quantum engine. 2025 Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2025: 1 doi: 10.23919/VLSITechnologyandCir65189.2025.11075179
[16]	Banerjee U, Pathak A, Chandrakasan A P. An energy-efficient configurable lattice cryptography processor for the quantum-secure Internet of Things. 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 2019: 46 doi: 10.1109/ISSCC.2019.8662528
[17]	Ghosh A, Mera J M B, Karmakar A, et al. A 334uW 0.158mm² saber learning with rounding based post-quantum crypto accelerator. 2022 IEEE Custom Integrated Circuits Conference (CICC), 2022: 1 doi: 10.1109/CICC53496.2022.9772859
[18]	Kim B, Park J, Moon S, et al. Configurable energy-efficient lattice-based post-quantum cryptography processor for IoT devices. ESSCIRC 2022-IEEE 48th European Solid State Circuits Conference (ESSCIRC). 2022: 525 doi: 10.1109/ESSCIRC55480.2022.9911531
[19]	Li A B, Lu J H, Liu D S, et al. A 273μW 0.34mm² efficient CRYSTALS-KYBER processor for PQC towards edge computing. 2024 IEEE European Solid-State Electronics Research Conference (ESSERC), 2024: 472 doi: 10.1109/ESSCIRC55480.2022.9911531
[20]	Lee H, Kwon H, Lee Y. A 2.7-to-13.3μJ/boot/slot flexible RNS-CKKS processor in 28nm CMOS technology for FHE-based privacy-preserving computing. 2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024: 296 doi: 10.1109/ISSCC49657.2024.10454420
[21]	Lu S J, Zhu W P, Yang B H, et al. A 28nm 4.05µJ/encryption 8.72kHMul/s reconfigurable multi-scheme fully homomorphic encryption processor for encrypted client-server computing. 2025 IEEE International Solid-State Circuits Conference (ISSCC), 2025: 1 doi: 10.1109/ISSCC49661.2025.10904812
[22]	Shi G M, Tan Z H, Cao D P, et al. A 28nm 68MOPS 0.18µJ/Op paillier homomorphic encryption processor with bit-serial sparse ciphertext computing. 2023 IEEE International Solid-State Circuits Conference (ISSCC), 2023: 242 doi: 10.1109/ISSCC42615.2023.10067522
[23]	Lin L H, Yang Y K, Yang C H. A 30.4GOPS/mW MK-CKKS processor for secure multi-party computation. 2025 IEEE International Solid-State Circuits Conference (ISSCC). 2025: 296 doi: 10.1109/ISSCC49661.2025.10904776
[24]	Zhang R L, Wang X Y, Liu K Y, et al. A 0.186-pJ per bit latch-based true random number generator featuring mismatch compensation and random noise enhancement. IEEE J Solid State Circuits, 2022, 57(8): 2498 doi: 10.1109/JSSC.2021.3137312
[25]	Lee J, Lee J, Youn Y, et al. A 1.7 pJ/bit 10 MHz calibration-free PVT variation and mismatch tolerant latch-based true random number generator in 4 nm FinFET. 2025 Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2025: 1 doi: 10.23919/VLSITechnologyandCir65189.2025.11075211
[26]	Kim J, Chae H. A 10-Gb/s true random number generator using ML-resistant middle square method. IEEE J Solid State Circuits, 2024, 59(7): 2321 doi: 10.1109/JSSC.2023.3346428
[27]	Hao J C, Zhuang Q S, Zhang J H, et al. A 98fJ/bit current-starved-ring-oscillator-based TRNG with high PVT tolerance and resilience to frequency injection attack up to 1V. 2024 IEEE Custom Integrated Circuits Conference (CICC), 2024: 1 doi: 10.1109/CICC60959.2024.10528979

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Received: 20 April 2026 Revised: 28 April 2026 Online: Accepted Manuscript: 09 June 2026Uncorrected proof: 10 June 2026Published: 01 July 2026

Article Navigation > Journal of Semiconductors > 2026 > 47(7): 070201

Wenping Zhu, Hanning Wang, Bohan Yang, Leibo Liu. Towards secure computation and trusted silicon: emerging trends in ISSCC 2026 hardware security[J]. Journal of Semiconductors, 2026, 47(7): 070201. doi: 10.1088/1674-4926/26040035 ****W P Zhu, H N Wang, B H Yang, and L B Liu, Towards secure computation and trusted silicon: emerging trends in ISSCC 2026 hardware security[J]. J. Semicond., 2026, 47(7): 070201 doi: 10.1088/1674-4926/26040035

Citation:

Wenping Zhu, Hanning Wang, Bohan Yang, Leibo Liu. Towards secure computation and trusted silicon: emerging trends in ISSCC 2026 hardware security[J]. Journal of Semiconductors, 2026, 47(7): 070201. doi: 10.1088/1674-4926/26040035 ****

W P Zhu, H N Wang, B H Yang, and L B Liu, Towards secure computation and trusted silicon: emerging trends in ISSCC 2026 hardware security[J]. J. Semicond., 2026, 47(7): 070201 doi: 10.1088/1674-4926/26040035

Citation:

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Towards secure computation and trusted silicon: emerging trends in ISSCC 2026 hardware security

DOI: 10.1088/1674-4926/26040035

CSTR: 32376.14.1674-4926.26040035

Wenping Zhu^{1, 2, 3},
Hanning Wang^{1, 2, 3},
Bohan Yang^{1, 2, 3},
Leibo Liu^{1, 2, 3,}

1.
School of Integrated Circuits, Tsinghua University, Beijing 100084, China
2.
State Key Laboratory of Cryptography and Digital Economy Security, Tsinghua University, Beijing 100084, China
3.
Beijing National Research Center for Information Science and Technology (BNRist), Tsinghua University, Beijing 100084, China

More Information

Wenping Zhu received the B.S. degree from the School of Microelectronics, Xidian University, Xi’an, China, in 2008, and the Ph.D. degree from the Institute of Microelectronics, Tsinghua University, Beijing, China, in 2016. He is currently a Senior Engineer with the School of Integrated Circuits, Tsinghua University. His main research interests include mobile computing and VLSI SoC design, and cryptographic accelerators
Hanning Wang received the B.S. degree in network engineering and the M.S. degree in computer science and technology from China University of Geosciences, Wuhan, China, in 2009 and 2012, respectively. He is currently an Engineer with the School of Integrated Circuits, Tsinghua University, Beijing, China. His current research interests include hardware security and cryptographic engineering
Bohan Yang received the B.S. degree from Xi’an Jiaotong University, Xi’an, China, in 2003, the joint M.S. degree from Tsinghua University, Beijing, China, and KU Leuven, Leuven, Belgium, in 2012, and the Ph.D. degree in EE from KU Leuven in 2018. From 2018 to 2024, he was a Post-Doctoral Researcher with Tsinghua University, where he has been an Assistant Researcher with the School of Integrated Circuits since 2024. His research interests include cryptographic chips, embedded security, true random number generators (TRNGs), and physical unclonable functions (PUFs)
Leibo Liu received the B.S. degree in electronic engineering from Tsinghua University, Beijing, China, in 1999, and the Ph.D. degree from the Institute of Microelectronics, Tsinghua University in 2004. He is currently a Professor with the School of Integrated Circuits, Tsinghua University. His current research interests include reconfigurable computing, cryptographic processors, hardware security, and very large-scale integration digital signal processing
Corresponding author: liulb@tsinghua.edu.cn
Received Date: 2026-04-20
Revised Date: 2026-04-28

Available Online: 2026-06-09

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