A low-noise PLL design achieved by optimizing the loop bandwidth

Bai Chuang; Zhao Zhenyu; Zhang Minxuan

doi:10.1088/1674-4926/30/8/085011

J. Semicond. > 2009, Volume 30 > Issue 8 > 085011

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A low-noise PLL design achieved by optimizing the loop bandwidth

Bai Chuang, Zhao Zhenyu and Zhang Minxuan

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DOI: 10.1088/1674-4926/30/8/085011

Abstract: This paper describes a low-noise phase-locked loop (PLL) design method to achieve minimum jitter. Based on the phase noise properties extracted from the transistor, and the low-pass or high-pass transfer characteristics of different noise sources to the output, an optimal loop bandwidth design method, derived from a continuous time PLL model, further improves the jitter characteristics of the PLL. The described method not only finds the optimal loop-bandwidth to minimize the overall PLL jitter, but also achieves optimal loop-bandwidth by changing the value of the resistor or charge pump current. In addition, a phase-domain behavioral model in ADS is presented for accurately predicting improved jitter performance of a PLL at system level. A prototype PLL designed in a 0.18 µm CMOS technology is used to investigate the accuracy of the theoretical predictions. The simulation shows significant performance improvement by using the proposed method. The simulated RMS and peak-to-peak jitter ofthe PLL at the optimal loop-bandwidth are 10.262 ps and 46.851 ps, respectively.

Key words: continue-time domain analysis, optimal loop bandwidth, phase-domain behavioral model, timing jitter

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Bai Chuang, Zhao Zhenyu, Zhang Minxuan. A low-noise PLL design achieved by optimizing the loop bandwidth[J]. Journal of Semiconductors, 2009, 30(8): 085011. doi: 10.1088/1674-4926/30/8/085011

Bai C, Zhao Z Y, Zhang M X. A low-noise PLL design achieved by optimizing the loop bandwidth[J]. J. Semicond., 2009, 30(8): 085011. doi: 10.1088/1674-4926/30/8/085011.

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Received: 18 August 2015 Revised: 23 March 2009 Online: Published: 01 August 2009

This paper describes a low-noise phase-locked loop (PLL) design method to achieve minimum jitter. Based on the phase noise properties extracted from the transistor, and the low-pass or high-pass transfer characteristics of different noise sources to the output, an optimal loop bandwidth design method, derived from a continuous time PLL model, further improves the jitter characteristics of the PLL. The described method not only finds the optimal loop-bandwidth to minimize the overall PLL jitter, but also achieves optimal loop-bandwidth by changing the value of the resistor or charge pump current. In addition, a phase-domain behavioral model in ADS is presented for accurately predicting improved jitter performance of a PLL at system level. A prototype PLL designed in a 0.18 µm CMOS technology is used to investigate the accuracy of the theoretical predictions. The simulation shows significant performance improvement by using the proposed method. The simulated RMS and peak-to-peak jitter ofthe PLL at the optimal loop-bandwidth are 10.262 ps and 46.851 ps, respectively.

A low-noise PLL design achieved by optimizing the loop bandwidth

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