J. Semicond. > 2009, Volume 30 > Issue 8 > 086001

SEMICONDUCTOR TECHNOLOGY

Wafer level hermetic packaging based on Cu–Sn isothermal solidification technology

Cao Yuhan and Luo Le

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DOI: 10.1088/1674-4926/30/8/086001

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Abstract: A novel wafer level bonding method based on Cu–Sn isothermal solidification technology is established. A multi-layer sealing ring and the bonding processing are designed, and the amount of solder and the bonding parameters are optimized based on both theoretical and experimental results. Verification shows that oxidation of the solder layer, voids and the scalloped-edge appearance of the Cu6Sn5 phase are successfully avoided. An average shear strength of 19.5 MPa and an excellent leak rate of around 1.9 × 10-9 atm cc/s are possible, meeting the demandsof MIL-STD-883E.

Key words: wafer level package; Cu–Sn isothermal solidification technology; hermeticity

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    Received: 18 August 2015 Revised: 07 April 2009 Online: Published: 01 August 2009

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      Article Navigation >  Journal of Semiconductors  > 2009  >  30(8): 086001
      Cao Yuhan, Luo Le. Wafer level hermetic packaging based on Cu–Sn isothermal solidification technology[J]. Journal of Semiconductors, 2009, 30(8): 086001. doi: 10.1088/1674-4926/30/8/086001 ****Cao Y H, Luo L. Wafer level hermetic packaging based on Cu–Sn isothermal solidification technology[J]. J. Semicond., 2009, 30(8): 086001. doi:  10.1088/1674-4926/30/8/086001.
      Citation:
      Cao Yuhan, Luo Le. Wafer level hermetic packaging based on Cu–Sn isothermal solidification technology[J]. Journal of Semiconductors, 2009, 30(8): 086001. doi: 10.1088/1674-4926/30/8/086001 ****
      Cao Y H, Luo L. Wafer level hermetic packaging based on Cu–Sn isothermal solidification technology[J]. J. Semicond., 2009, 30(8): 086001. doi:  10.1088/1674-4926/30/8/086001.
      shu

      Wafer level hermetic packaging based on Cu–Sn isothermal solidification technology

      DOI: 10.1088/1674-4926/30/8/086001

      • State Key Laboratories of Transducer Technology, Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai 200050, China

      • State Key Laboratories of Transducer Technology, Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai 200050, China

      • Received Date: 2015-08-18
      • Accepted Date: 2009-02-17
      • Revised Date: 2009-04-07
      • Published Date: 2009-07-31

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