A high performance 90 nm CMOS SAR ADC with hybrid architecture

Tong Xingyuan; Chen Jianming; Zhu Zhangming; Yang Yintang

doi:10.1088/1674-4926/31/1/015002

J. Semicond. > 2010, Volume 31 > Issue 1 > 015002

SEMICONDUCTOR INTEGRATED CIRCUITS

A high performance 90 nm CMOS SAR ADC with hybrid architecture

Tong Xingyuan^1,, Chen Jianming², Zhu Zhangming¹ and Yang Yintang¹

+ Author Affiliations

DOI: 10.1088/1674-4926/31/1/015002

Abstract: A 10-bit 2.5 MS/s SAR A/D converter is presented. In the circuit design, an R-C hybrid architecture D/A converter, pseudo-differential comparison architecture and low power voltage level shifters are utilized. Design challenges and considerations are also discussed. In the layout design, each unit resistor is sided by dummies for good matching performance, and the capacitors are routed with a common-central symmetry method to reduce the nonlinearity error. This proposed converter is implemented based on 90 nm CMOS logic process. With a 3.3 V analog supply and a 1.0 V digital supply, the differential and integral nonlinearity are measured to be less than 0.36 LSB and 0.69 LSB respectively. With an input frequency of 1.2 MHz at 2.5 MS/s sampling rate, the SFDR and ENOB are measured to be 72.86 dB and 9.43 bits respectively, and the power dissipation is measured to be 6.62 mW including the output drivers. This SAR A/D converter occupies an area of 238×214 μm2. The design results of this converter show that it is suitable for multi-supply embedded SoC applications.

Key words: analog-to-digital converter, CMOS integrated circuits, level shifters, multi-supply SoC, high performance

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Received: 18 August 2015 Revised: 27 July 2009 Online: Published: 01 January 2010

A 10-bit 2.5 MS/s SAR A/D converter is presented. In the circuit design, an R-C hybrid architecture D/A converter, pseudo-differential comparison architecture and low power voltage level shifters are utilized. Design challenges and considerations are also discussed. In the layout design, each unit resistor is sided by dummies for good matching performance, and the capacitors are routed with a common-central symmetry method to reduce the nonlinearity error. This proposed converter is implemented based on 90 nm CMOS logic process. With a 3.3 V analog supply and a 1.0 V digital supply, the differential and integral nonlinearity are measured to be less than 0.36 LSB and 0.69 LSB respectively. With an input frequency of 1.2 MHz at 2.5 MS/s sampling rate, the SFDR and ENOB are measured to be 72.86 dB and 9.43 bits respectively, and the power dissipation is measured to be 6.62 mW including the output drivers. This SAR A/D converter occupies an area of 238×214 μm2. The design results of this converter show that it is suitable for multi-supply embedded SoC applications.

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