Short locking time and low jitter phase-locked loop based on slope charge pump control

Guo Zhongjie; Liu Youbao; Wu Longsheng; Wang Xihu; Tang Wei

doi:10.1088/1674-4926/31/10/105002

J. Semicond. > 2010, Volume 31 > Issue 10 > 105002

SEMICONDUCTOR INTEGRATED CIRCUITS

Short locking time and low jitter phase-locked loop based on slope charge pump control

Guo Zhongjie, Liu Youbao, Wu Longsheng, Wang Xihu and Tang Wei

+ Author Affiliations

DOI: 10.1088/1674-4926/31/10/105002

Abstract: A novel structure of a phase-locked loop (PLL) characterized by a short locking time and low jitter is presented, which is realized by generating a linear slope charge pump current dependent on monitoring the output of the phase frequency detector (PFD) to implement adaptive bandwidth control. This improved PLL is created by utilizing a fast start-up circuit and a slope current control on a conventional charge pump PLL. First, the fast start-up circuit is enabled to achieve fast pre-charging to the loop filter. Then, when the output pulse of the PFD is larger than a minimum value, the charge pump current is increased linearly by the slope current control to ensure a shorter locking time and a lower jitter. Additionally, temperature variation is attenuated with the temperature compensation in the charge pump current design. The proposed PLL has been fabricated in a kind of DSP chip based on a 0.35 μm CMOS process. Comparing the characteristics with the classical PLL, the proposed PLL shows that it can reduce the locking time by 60% with a low peak-to-peak jitter of 0.3% at a wide operation temperature range.

Key words: phase-locked loop, loop bandwidth, phase margin, phase frequency detector, slope charge pump current

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Received: 18 August 2015 Revised: 13 May 2010 Online: Published: 01 October 2010

A novel structure of a phase-locked loop (PLL) characterized by a short locking time and low jitter is presented, which is realized by generating a linear slope charge pump current dependent on monitoring the output of the phase frequency detector (PFD) to implement adaptive bandwidth control. This improved PLL is created by utilizing a fast start-up circuit and a slope current control on a conventional charge pump PLL. First, the fast start-up circuit is enabled to achieve fast pre-charging to the loop filter. Then, when the output pulse of the PFD is larger than a minimum value, the charge pump current is increased linearly by the slope current control to ensure a shorter locking time and a lower jitter. Additionally, temperature variation is attenuated with the temperature compensation in the charge pump current design. The proposed PLL has been fabricated in a kind of DSP chip based on a 0.35 μm CMOS process. Comparing the characteristics with the classical PLL, the proposed PLL shows that it can reduce the locking time by 60% with a low peak-to-peak jitter of 0.3% at a wide operation temperature range.

Short locking time and low jitter phase-locked loop based on slope charge pump control

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Short locking time and low jitter phase-locked loop based on slope charge pump control

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Short locking time and low jitter phase-locked loop based on slope charge pump control

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