
SEMICONDUCTOR INTEGRATED CIRCUITS
Guo Zhongjie, Liu Youbao, Wu Longsheng, Wang Xihu and Tang Wei
Abstract: A novel structure of a phase-locked loop (PLL) characterized by a short locking time and low jitter is presented, which is realized by generating a linear slope charge pump current dependent on monitoring the output of the phase frequency detector (PFD) to implement adaptive bandwidth control. This improved PLL is created by utilizing a fast start-up circuit and a slope current control on a conventional charge pump PLL. First, the fast start-up circuit is enabled to achieve fast pre-charging to the loop filter. Then, when the output pulse of the PFD is larger than a minimum value, the charge pump current is increased linearly by the slope current control to ensure a shorter locking time and a lower jitter. Additionally, temperature variation is attenuated with the temperature compensation in the charge pump current design. The proposed PLL has been fabricated in a kind of DSP chip based on a 0.35 μm CMOS process. Comparing the characteristics with the classical PLL, the proposed PLL shows that it can reduce the locking time by 60% with a low peak-to-peak jitter of 0.3% at a wide operation temperature range.
Key words: phase-locked loop, loop bandwidth, phase margin, phase frequency detector, slope charge pump current
1 |
A fast-locking bang-bang phase-locked loop with adaptive loop gain controller Jincheng Yang, Zhao Zhang, Nan Qi, Liyuan Liu, Jian Liu, et al. Journal of Semiconductors, 2018, 39(12): 125002. doi: 10.1088/1674-4926/39/12/125002 |
2 |
A monolithic K-band phase-locked loop for microwave radar application Guangyao Zhou, Shunli Ma, Ning Li, Fan Ye, Junyan Ren, et al. Journal of Semiconductors, 2017, 38(2): 025002. doi: 10.1088/1674-4926/38/2/025002 |
3 |
Design of improved CMOS phase-frequency detector and charge-pump for phase-locked loop Faen Liu, Zhigong Wang, Zhiqun Li, Qin Li, Sheng Chen, et al. Journal of Semiconductors, 2014, 35(10): 105006. doi: 10.1088/1674-4926/35/10/105006 |
4 |
A wide-band low phase noise LC-tuned VCO with constant KVCO/ωosc for LTE PLL Huang Jiwei, Wang Zhigong, Li Kuili, Li Zhengping, Wang Yongping, et al. Journal of Semiconductors, 2012, 33(2): 025008. doi: 10.1088/1674-4926/33/2/025008 |
5 |
Low power fast settling multi-standard current reusing CMOS fractional-N frequency synthesizer Lou Wenfeng, Feng Peng, Wang Haiyong, Wu Nanjian Journal of Semiconductors, 2012, 33(4): 045004. doi: 10.1088/1674-4926/33/4/045004 |
6 |
Pan Yaohua, Mei Niansong, Chen Hu, Huang Yumei, Hong Zhiliang, et al. Journal of Semiconductors, 2012, 33(1): 015001. doi: 10.1088/1674-4926/33/1/015001 |
7 |
A low spur, low jitter 10-GHz phase-locked loop in 0.13-μm CMOS technology Mei Niansong, Sun Yu, Lu Bo, Pan Yaohua, Huang Yumei, et al. Journal of Semiconductors, 2011, 32(3): 035004. doi: 10.1088/1674-4926/32/3/035004 |
8 |
A 2.4 GHz high-linearity low-phase-noise CMOS LC-VCO based on capacitance compensation Li Zhenrong, Zhuang Yiqi, Li Bing, Jin Gang, Jin Zhao, et al. Journal of Semiconductors, 2010, 31(7): 075005. doi: 10.1088/1674-4926/31/7/075005 |
9 |
A low-power and low-phase-noise LC digitally controlled oscillator featuring a novel capacitor bank Tian Huanhuan, Li Zhiqiang, Chen Pufeng, Wu Rufei, Zhang Haiying, et al. Journal of Semiconductors, 2010, 31(12): 125003. doi: 10.1088/1674-4926/31/12/125003 |
10 |
A low-phase-noise digitally controlled crystal oscillator for DVB TV tuners Zhao Wei, Lu Lei, Tang Zhangwen Journal of Semiconductors, 2010, 31(7): 075003. doi: 10.1088/1674-4926/31/7/075003 |
11 |
A 0.8 V low power low phase-noise PLL Han Yan, Liang Xiao, Zhou Haifeng, Xie Yinfang, Wong Waisum, et al. Journal of Semiconductors, 2010, 31(8): 085009. doi: 10.1088/1674-4926/31/8/085009 |
12 |
A 0.5–1.7 GHz low phase noise ring-oscillator-based PLL for mixed-signal SoCs Jiao Yishu, Zhou Yumei, Jiang Jianhua, Wu Bin Journal of Semiconductors, 2010, 31(9): 095002. doi: 10.1088/1674-4926/31/9/095002 |
13 |
A multiple-pass ring oscillator based dual-loop phase-locked loop Chen Danfeng, Ren Junyan, Deng Jingjing, Li Wei, Li Ning, et al. Journal of Semiconductors, 2009, 30(10): 105014. doi: 10.1088/1674-4926/30/10/105014 |
14 |
Low-power wide-locking-range injection-locked frequency divider for OFDM UWB systems Yin Jiangwei, Li Ning, Zheng Renliang, Li Wei, Ren Junyan, et al. Journal of Semiconductors, 2009, 30(5): 055003. doi: 10.1088/1674-4926/30/5/055003 |
15 |
An enhanced close-in phase noise LC-VCO using parasitic V-NPN transistors in a CMOS process Gao Peijun, Oh N J, Min Hao Journal of Semiconductors, 2009, 30(8): 085004. doi: 10.1088/1674-4926/30/8/085004 |
16 |
A low-noise PLL design achieved by optimizing the loop bandwidth Bai Chuang, Zhao Zhenyu, Zhang Minxuan Journal of Semiconductors, 2009, 30(8): 085011. doi: 10.1088/1674-4926/30/8/085011 |
17 |
A 3.96 GHz phase-locked loop for mode-1 MB-OFDM UWB hopping carrier generation Zheng Yongzheng, Li Weinan, Xia Lingli, Huang Yumei, Hong Zhiliang, et al. Journal of Semiconductors, 2009, 30(7): 075003. doi: 10.1088/1674-4926/30/7/075003 |
18 |
CMOS Implementation of a Wideband Low Phase Noise PLL Frequency Synthesizer Chen Zuotian, Wu Xuan, Tang Shoulong, Wu Jianhui Chinese Journal of Semiconductors , 2006, 27(10): 1838-1843. |
19 |
Tang Lu, Wang Zhigong, Huang Ting, Li Zhiqun Chinese Journal of Semiconductors , 2006, 27(3): 459-466. |
20 |
Low Phase Noise Quadrature Oscillators Using New Injection Locked Technique Chinese Journal of Semiconductors , 2005, 26(9): 1705-1710. |
Article views: 4253 Times PDF downloads: 5562 Times Cited by: 0 Times
Received: 18 August 2015 Revised: 13 May 2010 Online: Published: 01 October 2010
Citation: |
Guo Zhongjie, Liu Youbao, Wu Longsheng, Wang Xihu, Tang Wei. Short locking time and low jitter phase-locked loop based on slope charge pump control[J]. Journal of Semiconductors, 2010, 31(10): 105002. doi: 10.1088/1674-4926/31/10/105002
****
Guo Z J, Liu Y B, Wu L S, Wang X H, Tang W. Short locking time and low jitter phase-locked loop based on slope charge pump control[J]. J. Semicond., 2010, 31(10): 105002. doi: 10.1088/1674-4926/31/10/105002.
|
Journal of Semiconductors © 2017 All Rights Reserved 京ICP备05085259号-2