Optically stimulated luminescence (OSL) is the luminescence emitted from a semiconductor during its exposure to light. The OSL intensity is a function of the total dose absorbed by the sample. The dose-rate dependence of the OSL signal of the semiconductor CaS doped Ce and Sm was studied by numerical simulation and experiments. Based on a one-trap/one-center model, the whole OSL process was represented by a series of differential equations. The dose-rate properties of the materials were acquired theoretically by solving the equations. Good coherence was achieved between numerical simulation and experiments, both of which showed that the OSL signal was independent of dose rate. This result validates that when using OSL as a dosimetry technique, the dose-rate effect can be neglected.

Ga₂O₃/ITO films were prepared by magnetron sputtering on quartz glass substrates. The transmittance and sheet resistance of ITO films and Ga₂O₃/ITO films were measured by using a double beam spectrophotometer and four point probes. The effect of the ITO layer and Ga₂O₃ layer thickness on the electrical and optical properties of Ga₂O₃/ITO bi-layer films were investigated in detail. Ga₂O₃ (50 nm)/ITO (23 nm) films exhibited a low sheet resistance of 323 Ω/□ and high deep ultraviolet transmittance of 77.6% at a wavelength of 280 nm. The ITO layer controls the ultraviolet transmittance and sheet resistance of Ga₂O₃/ITO films. The Ga₂O₃ layer thickness has a marked effect on the transmission spectral shape of Ga₂O₃/ITO films in the violet spectral region.

A series of n-ZnO/n-SiC/p-Si and n-ZnO/p-Si heterojunctions were prepared by DC sputtering. Their structural properties, I–V curves, photovoltaic effects and photo-response spectra were studied. The photoelectric conversion characteristics of n-ZnO/n-SiC/p-Si and n-ZnO/p-Si heterojunctions were investigated. It is found that the photoelectric conversion efficiency of the n-ZnO/n-SiC/p-Si heterojunction is about four times higher than that of the n-ZnO/p-Si heterojunction. The photovoltaic response spectrum indicated that the photoresponse curve of n-ZnO/n-SiC/p-Si increased more strongly than that of n-ZnO/p-Si with the wavelength increasing. It shows that the photoresponse of n-ZnO/p-Si can be enhanced when inserting a 3C-SiC layer between ZnO and Si. There is one inflexion in the photocurrent response curve of the n-ZnO/p-Si heterojunction and two inflexions in that of the n-ZnO/n-SiC/p-Si heterojunction. It is clear that the 3C-SiC plays an important role in the photoelectric conversion of the n-ZnO/n-SiC/p-Si heterojunction.

A solar cell with a novel structure is investigated by means of the analysis of microelectronic and photonic structure (AMPS). The power conversion efficiency is investigated with the variations in interface recombination velocity, thicknesses of p-type layer, intrinsic layer, n-type layer, and doping density. Results show that it is available and preferable in theory to employ a-SiC:H as a window layer in p-a-SiC:H/i-a-Si:H/n-μc-Si solar cells, and provide a new approach to improving the power conversion efficiency of amorphous silicon solar cells.

An attempt has been made to give a detailed review of strained silicon technology. Various device models have been studied that consider the effect of strain on the devices, and comparisons have been drawn. A review of some modeling issues in strained silicon technology has also been outlined. The review indicates that this technology is very much required in nanoscale MOSFETs due to its several potential benefits, and there is a strong need for an analytical model which describes the complete physics of the strain technology.

The method of multi-bias capacitance voltage measurement is presented. The physical meaning of gate-source and gate-drain capacitances in AlGaN/GaN HEMT and the variations in them with different bias conditions are discussed. A capacitance model is proposed to reflect the behaviors of the gate-source and gate-drain capacitances, which shows a good agreement with the measured capacitances, and the power performance obtains good results compared with the measured data from the capacitance model.

The thermal and electro stability of multi-finger heterojunction bipolar transistors (HBTs) with different structures were analyzed and discussed simultaneously. The thermal stability of the devices with different layout structures was assessed by the DC–IV test and thermal resistance calculation. Their electro stability was assessed by the calculation of the stability factor K based on the S parameter of the HBT. It is found that HBTs with higher thermal stability are prone to lower electro stability. The trade-off relationship between the two types of stability was explained and discussed by using a compact K-factor analytic formula which is derived from the small signal equivalent circuit model of HBT. The electro stability of the device with a thermal ballasting resistor was also discussed, based on the analytic formula.

An improved large-signal equivalent-circuit model for SiGe HBTs based on the MEXTRAM model (level 504.5) is proposed. The proposed model takes into account the soft knee effect. The model keeps the main features of the MEXTRAM model even though some simplifications have been made in the equivalent circuit topology. This model is validated in DC and AC analyses for SiGe HBTs fabricated with 0.35-μm BiCMOS technology, 1 × 8 μm² emitter area. Good agreement is achieved between the measured and modeled results for DC and S-parameters (from 50 MHz to 20 GHz), which shows that the proposed model is accurate and reliable. The model has been implemented in Verilog-A using the ADS circuit simulator.

Characteristics of a uni-traveling-carrier photodiode (UTC-PD) are investigated. A hydro-dynamic model is introduced which takes into account the electrons' velocity overshoot in the depletion region, which is a more accurate high speed device than using the normal drift–diffuse model. Based on previous results, two modified UTC-PDs are presented, and an optimized device is obtained, the bandwidth of which is more than twice that of the original.

The enhancement of the light output of an embedded photonic crystal light emitting diode is investigated based on the finite-difference time-domain modeling. The embedded photonic crystal (PC) lattice type, multi-layer embedded PC, distance between the multiple quantum well and the embedded PC are studied. It is found that the embedded one dimensional PC can act as well as embedded two dimensional PCs. The emitted light flux in the up direction can be increased by a new kind of multi-layer embedded PC. Also, we show that the light output in the up direction for the LED with both surfaces and embedded PC could be as high as five times that of a conventional LED.

In order to analyze the thermal characteristics of the cavity facet of a semiconductor laser, a home-built near-field scanning optical microscopy (NSOM) is employed to probe the topography of the facet. By comparing the topographic images of two samples under different DC current injections, we can find that the thermal characteristic is related to its lifetime. We show that it is possible to predict the lifetime of the semiconductor laser diode with non-destructive tests.

A new modified method based on the charge pumping technique is proposed and adopted to extract the lateral profiles of oxide charges in an advanced MOSFET. A 0.12 μm SONOS device with 50 nm threshold voltage peak is designed and utilized to demonstrate the proposed method. The trapped charge distribution with a narrow peak can be precisely characterized with this method, which shows good consistency with the measured threshold voltage.

In order to overcome the bit-to-bit interference of the traditional multi-level NAND type device, this paper firstly proposes a novel multi-bit non-uniform channel charge trapping memory (NUC-CTM) device with virtual-source NAND-type array architecture, which can effectively restrain the second-bit effect (SBE) and provide 3-bit per cell capability. Owing to the n^- buffer region, the SBE induced threshold voltage window shift can be reduced to less than 400 mV and the minimum threshold voltage window between neighboring levels is larger than 750 mV for reliable 3-bit operation. A silicon-rich SiON is also investigated as a trapping layer to improve the retention reliability of the NUC-CTM.

A MEMS compressed period-tunable grating device with a wide tuning range has been designed, fabricated and characterized. To increase the tuning range, avoid instability with tuning and improve the performance, we propose in this paper a period-tunable grating which is compressed by large-displacement comb actuators with tilted folded beams. The experimental results show that the designed grating device has a compression range of up to 144 μm within 37 V driving voltage. The period of the grating can be adjusted continuously from 16 to 14 μm with a tuning range of 12.5%. The maximum tuning range of the first-order diffraction angle is 0.34^o at 632.8 nm and the reflectivity of the grating is more than 92.6% in the mid-infrared region. The grating device can be fabricated by simple processes and finds applications in mid-infrared spectrometers.

A MEMS piezoresistive magnetic field sensor based on a silicon bridge structure has been simulated and tested. The sensor consists of a silicon sensitivity diaphragm embedded with a piezoresistive Wheatstone bridge, and a ferromagnetic magnet adhered to the sensitivity diaphragm. When the sensor is subjected to an external magnetic field, the magnetic force bends the silicon sensitivity diaphragm, producing stress and resistors change of the Wheatstone bridge and the output voltage of the sensor. Good agreement is observed between the theory and measurement behavior of the magnetic field sensor. Experimental results demonstrate that the maximum sensitivity and minimum resolution are 48 mV/T and 160 μT, respectively, making this device suitable for strong magnetic field measurement. Research results indicate that the sensor repeatability and dynamic response time are about 0.66% and 150 ms, respectively.

This paper presents a sense amplifier scheme for low-voltage embedded flash (eFlash) memory applications. The topology of the sense amplifier is based on current mode comparison. Moreover, an offset-voltage elimination technique is employed to improve the sensing performance under a small memory cell current. The proposed sense amplifier is designed based on a GSMC 130 nm eFlash process, and the sense time is 0.43 ns at 1.5 V, corresponding to a 46% improvement over the conventional technologies.

A novel structure of a phase-locked loop (PLL) characterized by a short locking time and low jitter is presented, which is realized by generating a linear slope charge pump current dependent on monitoring the output of the phase frequency detector (PFD) to implement adaptive bandwidth control. This improved PLL is created by utilizing a fast start-up circuit and a slope current control on a conventional charge pump PLL. First, the fast start-up circuit is enabled to achieve fast pre-charging to the loop filter. Then, when the output pulse of the PFD is larger than a minimum value, the charge pump current is increased linearly by the slope current control to ensure a shorter locking time and a lower jitter. Additionally, temperature variation is attenuated with the temperature compensation in the charge pump current design. The proposed PLL has been fabricated in a kind of DSP chip based on a 0.35 μm CMOS process. Comparing the characteristics with the classical PLL, the proposed PLL shows that it can reduce the locking time by 60% with a low peak-to-peak jitter of 0.3% at a wide operation temperature range.

A dual-band direct-conversion WLAN transceiver baseband compliant with the IEEE 802.11a/b/g standards is described. Several critical techniques for receiver DC offset compensation and transmitter carrier leakage rejection calibration are presented that enable the direct-conversion architecture to meet all WLAN specifications. The receiver baseband VGA provides 62 dB gain range with steps of 2 dB and a DC offset cancellation circuit is introduced to remove the offset from layout and self-mixing. The calibration loop achieves constant high-pass pole when gain changes; and a fast response time by programming the pole to 1 MHz during preamble and to 30 kHz during receiving data. The transmitter baseband employs an auto-calibration loop with on-chip AD and DA to suppress the carrier leakage, and AD can be powered down after calibration to save power consumption. The chip consumes 17.52 mA for RX baseband VGA and DCOC, and 8.3 mA for TX carrier leakage calibration (5.88 mA after calibration) from 2.85 V supply. Implemented in a 0.35 μm SiGe technology, they occupy 0.68 mm² and 0.18 mm² die size respectively.

A continuously tunable gain and bandwidth analog front-end for ambulatory biopotential measurement systems is presented. The front-end circuit is capable of amplifying and conditioning different biosignals. To optimize the power consumption and simplify the system architecture, the front-end only adopts two-stage amplifiers. In addition, careful design eliminates the need for chopping circuits. The input-referred noise of the system is only 1.19 μVrms (0.48–2000 Hz). The chip is fabricated via a SMIC 0.18 μm CMOS process. Although the power consumption is only 32.1 μW under a 3 V voltage supply, test results show that the chip can successfully extract biopotential signals.

A fully integrated VCO and divider implemented in SMIC 0.13-μm RFCMOS 1P8M technology with a 1.2 V supply voltage is presented. The frequency of the VCO is tuning from 8.64 to 11.62 GHz while the quadrature LO signals for 802.11a WLAN in 5.8 GHz band or for 802.11b/g WLAN and Bluetooth in 2.4 GHz band can be obtained by a frequency division by 2 or 4, respectively. A 6 bit switched capacitor array is applied for precise tuning of all necessary frequency bands. The testing results show that the VCO has a phase noise of –113 dBc @ 1 MHz offset from the carrier of 5.5 GHz by dividing VCO output by two and the VCO core consumes 3.72 mW. The figure-of-merit for the tuning-range (FOM_T) of the VCO is –192.6 dBc/Hz.

A 12-bit intrinsic accuracy digital-to-analog converter integrated into standard digital 0.18 μm CMOS technology is proposed. It is based on a current steering segmented 6+6 architecture and requires no calibration. By dividing one most significant bit unary source into 16 elements located in 16 separated regions of the array, the linear gradient errors and quadratic errors can be averaged and eliminated effectively. A novel static performance testing method is proposed. The measured differential nonlinearity and integral nonlinearity are 0.42 and 0.39 least significant bit, respectively. For 12-bit resolution, the converter reaches an update rate of 100 MS/s. The chip operates from a single 1.8 V voltage supply, and the core die area is 0.28 mm².

This paper presents a novel high-speed low voltage differential signaling (LVDS) driver design for point-to-point communication. The switching noise of the driver was greatly suppressed by adding a charge/discharge circuit and the operating frequency of the circuit was also increased. A simple and effective common-mode feedback circuit was added to stabilize the output common-mode voltage. The proposed driver was implemented in a standard 0.35 μm CMOS process with a die area of 0.15 mm². The test result shows that the proposed driver works well at 2.2 Gbps with power consumption of only 23 mW and 21.35 ps peak-to-peak jitter under a 1.8 V power supply.

The frame structure of a process design kit (PDK) is described in detail, and a practical design method for PDK is presented. Based on this method, a useful SMIC 65 nm PDK has been successfully designed and realized, which is applicable to native EDA software of Zeni. The design process and difficulties of PDK are introduced by developing and analyzing these parameterized cell (Pcell) devices (MOS, resistor, etc.). A structured design method was proposed to implement Pcell, which makes thousands upon thousands of source codes of Pcell concise, readable, easy-to-upkeep and transplantable. Moreover, a Pcase library for each Pcell is designed to verify the Pcell in batches. By this approach, the Pcell can be verified efficiently and the PDK will be more reliable and steady. In addition, the component description format parameters and layouts of the Pcell are optimized by adding flexibility and improving performance, which benefits analog and custom IC designers to satisfy the demand of design. Finally, the SMIC 65 nm PDK was applied to IC design. The results indicate that the SMIC 65 nm PDK is competent to support IC design.

Based on a 5 MSBs (most-significant-bits)-plus-5 LSBs (least-significant-bits) C–R hybrid D/A conversion and low-offset pseudo-differential comparison approach, with capacitor array axially symmetric layout topology and resistor string low gradient mismatch placement method, an 8-channel 10-bit 200-kS/s SAR ADC (successive-approximation-register analog-to-digital converter) IP core for a touch screen SoC (system-on-chip) is implemented in a 0.18 μm 1P5M CMOS logic process. Design considerations for the touch screen SAR ADC are included. With a 1.8 V power supply, the DNL (differential non-linearity) and INL (integral non-linearity) of this converter are measured to be about 0.32 LSB and 0.81 LSB respectively. With an input frequency of 91 kHz at 200- kS/s sampling rate, the spurious-free dynamic range and effective-number-of-bits are measured to be 63.2 dB and 9.15 bits respectively, and the power is about 136 μW. This converter occupies an area of about 0.08 mm². The design results show that it is very suitable for touch screen SoC applications.

The multi-SCCO₂ (supercritical carbon dioxide) release and dry process based on our specialized SCCO₂ semiconductor process equipment is investigated and the releasing mechanism is discussed. The experiment results show that stuck cantilever beams were held up again under SCCO₂ high pressure treatment and the repeatability of this process is nearly 100%.

Etching was performed on (100) silicon wafers using silicon-dissolved tetramethylammonium hydroxide (TMAH) solutions without the addition of surfactant. Experiments were carried out in different TMAH concentrations at different temperatures for different etching times. The surface phenomena, etching rates, surface morphology and surface reflectance were analyzed. Experimental results show that the resulting surface covered with uniform pyramids can be realized with a small change in etching rates during the etching process. The etching mechanism is explained based on the experimental results and the theoretical considerations. It is suggested that all the components in the TMAH solutions play important roles in the etching process. Moreover, TMA⁺ ions may increase the wettability of the textured surface. A good textured surface can be obtained in conditions where the absorption of OH^–/H₂O is in equilibrium with that of TMA⁺/SiO₂(OH)₂^2–.

With the use of a chemical-mechanical polishing (CMP) simulator verified by testing data from a foundry, the effect of dummy fill characteristics, such as fill size, fill density and fill shape, on CMP planarity is analyzed. The results indicate that dummy density has a significant impact on oxide erosion, and copper dishing is in proportion to dummy size. We also demonstrate that cross shape dummy fill can have the best dishing performance at the same density.

This paper presents a new cleaning process using boron-doped diamond (BDD) film anode electrochemical oxidation for metallic contaminants on polished silicon wafer surfaces. The BDD film anode electrochemical oxidation can efficiently prepare pyrophosphate peroxide, pyrophosphate peroxide can oxidize organic contaminants, and pyrophosphate peroxide is deoxidized into pyrophosphate. Pyrophosphate, a good complexing agent, can form a metal complex, which is a structure consisting of a copper ion, bonded to a surrounding array of two pyrophosphate anions. Three polished wafers were immersed in the 0.01 mol/L CuSO₄ solution for 2 h in order to make comparative experiments. The first one was cleaned by pyrophosphate peroxide, the second by RCA (Radio Corporation of America) cleaning, and the third by deionized (DI) water. The XPS measurement result shows that the metallic contaminants on wafers cleaned by the RCA method and by pyrophosphate peroxide is less than the XPS detection limits of 1 ppm. And the wafer's surface cleaned by pyrophosphate peroxide is more efficient in removing organic carbon residues than RCA cleaning. Therefore, BDD film anode electrochemical oxidation can be used for microelectronics cleaning, and it can effectively remove organic contaminants and metallic contaminants in one step. It also achieves energy saving and environmental protection.