Novel multi-bit non-uniform channel charge trapping memory device with virtual-source NAND flash array

Gu Haiming; Pan Liyang; Zhu Peng; Wu Dong; Zhang Zhigang; Xu Jun

doi:10.1088/1674-4926/31/10/104009

J. Semicond. > 2010, Volume 31 > Issue 10 > 104009

SEMICONDUCTOR DEVICES

Novel multi-bit non-uniform channel charge trapping memory device with virtual-source NAND flash array

Gu Haiming, Pan Liyang, Zhu Peng, Wu Dong, Zhang Zhigang and Xu Jun

+ Author Affiliations

DOI: 10.1088/1674-4926/31/10/104009

Abstract: In order to overcome the bit-to-bit interference of the traditional multi-level NAND type device, this paper firstly proposes a novel multi-bit non-uniform channel charge trapping memory (NUC-CTM) device with virtual-source NAND-type array architecture, which can effectively restrain the second-bit effect (SBE) and provide 3-bit per cell capability. Owing to the n^- buffer region, the SBE induced threshold voltage window shift can be reduced to less than 400 mV and the minimum threshold voltage window between neighboring levels is larger than 750 mV for reliable 3-bit operation. A silicon-rich SiON is also investigated as a trapping layer to improve the retention reliability of the NUC-CTM.

Key words: multi-bit storage

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Gu Haiming, Pan Liyang, Zhu Peng, Wu Dong, Zhang Zhigang, Xu Jun. Novel multi-bit non-uniform channel charge trapping memory device with virtual-source NAND flash array[J]. Journal of Semiconductors, 2010, 31(10): 104009. doi: 10.1088/1674-4926/31/10/104009

Gu H M, Pan L Y, Zhu P, Wu D, Zhang Z G, Xu J. Novel multi-bit non-uniform channel charge trapping memory device with virtual-source NAND flash array[J]. J. Semicond., 2010, 31(10): 104009. doi: 10.1088/1674-4926/31/10/104009.

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Received: 18 August 2015 Revised: 15 April 2010 Online: Published: 01 October 2010

In order to overcome the bit-to-bit interference of the traditional multi-level NAND type device, this paper firstly proposes a novel multi-bit non-uniform channel charge trapping memory (NUC-CTM) device with virtual-source NAND-type array architecture, which can effectively restrain the second-bit effect (SBE) and provide 3-bit per cell capability. Owing to the n^- buffer region, the SBE induced threshold voltage window shift can be reduced to less than 400 mV and the minimum threshold voltage window between neighboring levels is larger than 750 mV for reliable 3-bit operation. A silicon-rich SiON is also investigated as a trapping layer to improve the retention reliability of the NUC-CTM.

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