The growth by molecular beam epitaxy of high quality GaAs epilayers on nonmisoriented GaAs(111)B substrates is reported. Growth control of the GaAs epilayers is achieved via in situ, real time measurement of the specular beam intensity of reflection high-energy electron diffraction (RHEED). Static surface phase maps of GaAs(111)B have been generated for a variety of incident As flux and substrate temperature conditions. The dependence of GaAs(111)B surface reconstruction phases on growth parameters is discussed. The (√19 × √19) surface reconstruction is identified to be the optimum starting surface for the latter growth of mirror-smooth epilayers. Regimes of growth conditions are optimized in terms of the static surface phase diagram and the temporal RHEED intensity oscillations.

A model has been developed to study the effect of depletion and energy quantization at the poly-silicon/oxide interface on the behavior of a nanometer scale n-MOSFET. A model of inversion charge density, including the inversion layer quantization using the variation approach in the substrate, has also been produced. Using the exact calculations of the polygate potential under the depletion and quantization conditions, a C–V model has been developed. All the results have been compared with the numerical models reported in existing literature and they show good agreement.

This study presents the fabrication and characterization of novel surface-type capacitive humidity sensors using vanadyl phthalocyanine (VOPc) as the active material. The devices, which comprise three different thicknesses, have been fabricated using a thermal evaporator. A thin film of VOPc is deposited on thoroughly cleaned glass substrates with pre-patterned Ag electrodes. The capacitive effect of the samples under humidity has been investigated. Comparison of the samples with different thicknesses shows that the thinnest device seems more sensitive towards humidity. The humidity dependent capacitance properties of the sensor make it beneficial for use in commercial hygrometers.

The electronic transport properties of the armchair silicon carbide nanotube (SiCNT) are investigated by using the combined nonequilibrium Green's function method with density functional theory. In the equilibrium transmission spectrum of the nanotube, a transmission valley of about 2.12 eV is discovered around Fermi energy, which means that the nanotube is a wide band gap semiconductor and consistent with results of first principle calculations. More important, negative differential resistance is found in its current voltage characteristic. This phenomenon originates from the variation of density of states caused by applied bias voltage. These investigations are meaningful to modeling and simulation in silicon carbide nanotube electronic devices.

DC I–V output, small signal and an extensive large signal characterization (load-pull measurements) of a GaN HEMT on a SiC substrate with different gate widths of 100 μm and 1 mm have been carried out. From the small signal data, it has been found that the cutoff frequencies increase with gate width varying from 100 μm to 1 mm, owing to the reduced contribution of the parasitic effect. The devices investigated with different gate widths are enough to work in the C band and X band. The large signal measurements include the load-pull measurements and power sweep measurements at the C band (5.5 GHz) and X band (8 GHz). When biasing the gate voltage in class AB and selecting the source impedance, the optimum load impedances seen from the device for output power and PAE were localized in the load-pull map. The results of a power sweep at an 8 GHz biased various drain voltage demonstrate that a GaN HEMT on a SiC substrate has good thermal conductivity and a high breakdown voltage, and the CW power density of 10.16 W/mm was obtained. From the results of the power sweep measurement at 5.5 GHz with different gate widths, the actual scaling rules and heat effect on the large periphery device were analyzed, although the effects are not serious. The measurement results and analyses prove that a GaN HEMT on a SiC substrate is an ideal candidate for high-power amplifier design.

Based on the material characteristics and the operational principle of the double base epilayer BJTs, and according to the drift–diffusion and the carrier recombination theory, the common emitter current gain is calculated considering four recombination processes. Then its performance is analyzed under high temperature conditions. The results show that the emitter injection efficiency decreases due to an increase in the base ionization rate with increasing temperature. Meanwhile, the SiC/SiO₂ interface states and the quality of the passivation layer will affect the surface recombination velocity, and make an obvious current gain fall-off at a high collector current.

4H-SiC metal Schottky field effect transistors (MESFETs) and Schottky barrier diodes (SBDs) were irradiated at room temperature with 1 MeV neutrons. The highest neutron flux and gamma-ray total dose were 1 × 10¹⁵ n/cm² and 3.3 Mrad(Si), respectively. After a neutron flux of 1 × 10¹³ n/cm², the current characteristics of the MESFET had only slightly changed, and the Schottky contacts of the gate contacts and the Ni, Ti/4H-SiC SBDs showed no obvious degradation. To further increase the neutron flux, the drain current of the SiC MESFET decreased and the threshold voltage increased. φ_B of the Schottky gate contact decreased when the neutron flux was more than or equal to 2.5 × 10¹⁴ n/cm². SiC Schottky interface damage and radiation defects in the bulk material are mainly mechanisms for performance degradation of the experiment devices, and a high doping concentration of the active region will improve the neutron radiation tolerance.

A novel scalable model for multi-finger RF MOSFETs modeling is presented. All the parasitic components, including gate resistance, substrate resistance and wiring capacitance, are directly determined from the layout. This model is further verified using a standard 0.13 μm RF CMOS process with nMOSFETs of different numbers of gate fingers, with the per gate width fixed at 2.5 μm and the gate length at 0.13 μm. Excellent agreement between measured and simulated S-parameters from 100 MHz to 20 GHz demonstrate the validity of this model.

A novel trench field stop (TFS) IGBT with a super junction (SJ) floating layer (SJ TFS-IGBT) is proposed. This IGBT presents a high blocking voltage (> 1200 V), low on-state voltage drop and fast turn-off capability. A SJ floating layer with a high doping concentration introduces a new electric field peak at the anode side and optimizes carrier distribution, which will improve the breakdown voltage in the off-state and decrease the energy loss in the on-state/switching state for the SJ TFS-IGBT. A low on-state voltage (V_F) and a high breakdown voltage (BV) can be achieved by increasing the thickness of the SJ floating layer under the condition of exact charge balance. A low turn-off loss can be achieved by decreasing the concentration of the P-anode. Simulation results show that the BV is enhanced by 100 V, V_F is decreased by 0.33 V (at 100 A/cm²⁾ and the turn-off time is shortened by 60%, compared with conventional TFS-IGBTs.

The linear cofactor difference operator (LCDO) method, a direct parameter extraction method for general diodes, is presented. With the developed LCDO method, the extreme spectral characteristic of the diode voltage--current curves is revealed, and its extreme positions are related to the diode characteristic parameters directly. The method is applied to diodes with different sizes and temperatures, and the related characteristic parameters, such as reverse saturation current, series resistance and non-ideality factor, are extracted directly. The extraction result shows good agreement with the experimental data.

A new complementary interface charge island structure of SOI high voltage device (CNI SOI) and its model are presented. CNI SOI is characterized by equidistant high concentration n ⁺ -regions on the top and bottom interfaces of dielectric buried layers. When a high voltage is applied to the device, complementary hole and electron islands are formed on the two n ⁺ -regions on the top and bottom interfaces. The introduced interface charges effectively increase the electric field of the dielectric buried layer (E_I) and reduce the electric field of the silicon layer (E_S), which result in a high breakdown voltage (BV). The influence of structure parameters and its physical mechanism on breakdown voltage are investigated for CNI SOI. E_I = 731 V/μm and BV = 750 V are obtained by 2D simulation on a 1-μm-thick dielectric layer and 5-μm-thick top silicon layer. Moreover, enhanced field E_I and reduced field E_S by the accumulated interface charges reach 641.3 V/μm and 23.73 V/μm, respectively.

By using the wafer bonding technique and wet etching process, a wafer bonded thin film AlGaInP LED with wet etched n-AlGaInP surfaces was fabricated. The morphology of the etched surface exhibits a pyramid-like feature. The wafer was cut into 270 × 270 μm² chips and then packaged into TO-18 without epoxy resin. With 20-mA current injection, the light intensity and output power of LED-I with surface roughening respectively reach 315 mcd and 4.622 mW, which was 1.7 times higher than that of LED-II without surface roughening. The enhancement of output power in LED-I can be attributed to the pyramid-like surface, which not only reduces the total internal reflection at the semiconductor--air interface but also effectively guides more photons into the escape angle for emission from the LED device.

Room temperature, continuous-wave bistable operation is achieved in two-section 1.24 μm InAs quantum-dot (QD) lasers with integrated intracavity QD saturable absorbers (SA). It is found that the hysteresis width is narrowed with increasing reverse bias voltage, and broadened with increasing length of saturable absorber. This can be explained by the competition between QD absorption and electroabsorption in the SA section. In addition, a larger hysteresis width is realized than other reports so far, which can be attributed to a greater number of stacked layers of active region in our case. The experimental results can be explained by a modified threshold current model.

We present a design of three-dimensional (3D) silica on a silicon single-mode single-polarization waveguide (SMSPW) by taking into consideration the induced birefringence effect of the silica. This can cut off the TM mode and transmit the TE mode. The characteristics of the light propagating across the polarization maintaining waveguide were simulated by 3D beam propagation methods (3D-BPM). The result showed that the SMSPW has a high extinction ratio over 50 dB for the TM mode. Without increasing the complexity of the waveguide fabricating process, this structure can be used as a polarizer directly, and can also be integrated easily into other waveguide devices.

An analysis of a surface emitting distributed-feedback quantum cascade laser (DFB QCL) based on a surface-plasmon waveguide is presented. The second-order grating realized by the sole patterning of the top metal provides strong feedback. The analysis is based on a coupled-mode theory derived from exact Floquet-Bloch solutions of the infinite periodic structure. The surface outcoupling efficiency and threshold gain for the optimized device design are 43% and 12 cm^-1, respectively, which represent great improvements on the conventional dielectric waveguide based DFB QCL with typical values of 17.5% and 20 cm^-1.

A novel asymmetrical current-based sensing scheme for 1T1C FRAM is proposed, in which the two input transistors are not the same size and a feedback NMOS is added at the reference side of the sense amplifier. Compared with the conventional symmetrical scheme in Ref. [8], the proposed scheme increases the sense margin of the readout current by 53.9% and decreases the sensing power consumption by 14.1%, at the cost of an additional 7.89% area of the sensing scheme. An experimental FRAM prototype utilizing the proposed asymmetrical scheme is implemented in a 0.35 μm three metal process, in which the function of the prototype is verified.

This paper presents an 8-bit sub-threshold microprocessor which can be powered by an integrated photosensitive diode. With a custom designed sub-threshold standard cell library and 1 kbit sub-threshold SRAM design, the leakage power of 58 nW, dynamic power of 385 nW @ 165 kHz, EDP 13 pJ/inst and the operating voltage of 350 mV are achieved. Under a light of about 150 kLux, the microprocessor can run at a rate of up to 500 kHz. The microprocessor can be used for wireless-sensor-network nodes.

A CMOS analog equalizer is designed to meet the different high speed communication specifications, such as USB 2.0, PCI-E and rapid IO. The proposed circuit architecture could facilitate the wide frequency scale ranging from 1 to 3.125 Gbps by adjusting the locations of pole and zero, so that the circuit can change its response accordingly as the channel characteristic alters. In order to balance the parasitic capacitors in the internal point, symmetric switches are addressed to generate the equal load for differential signals. A prototype chip was fabricated in 0.13-μm 1P8M mix-signal CMOS technology. The actual area is 0.49 × 0.5 mm², and the analog equalizer operates up to 3.125 Gbps over 3 m RG-58 coaxial cable and 50 cm FR4-PCB trace. The overall power dissipation is approximately 14.4 mW.

In bandgap references, the effect caused by the input offset of the operational amplifier can be effectively reduced by the utilization of cascade bipolar junction transistors (BJTs). But in modern CMOS logic processes, due to the small value of β , the base--emitter path of BJTs has a significant streaming effect on the collector current, which leads to a large temperature drift for the reference voltage. To solve this problem, a base–emitter current compensation technique is proposed in a cascade BJT bandgap reference structure to calibrate the curvature of the output voltage to temperature. Experimental results based on the 0.13 μm logic CMOS process show that the reference voltage is 1.238 V and the temperature coefficient is 6.2 ppm/℃ within the range of -40 to 125 ℃.

A buck DC–DC switching regulator with high efficiency is implemented by automatically altering the modulation mode according to load current, and it can operate with an input range of 4.5 to 30 V. At light load current, the converter operates in skip mode. The converter enters PWM mode operation with increasing load current. It reduces the switching loss at light load and standby state, which results in prolonging battery lifetime and stand-by time. Meanwhile, externally adjustable soft-start minimizes the inrush supply current and avoids the overshoot of output voltage at initial startup. The regulator is fabricated by a 0.6 μm CDMOS process. The test results show that, under the condition of 3.3 V output, the efficiency is up to 64% at 5 mA and the maximum efficiency is 95.5%.

This paper describes a 10-bit, 50-MS/s pipelined A/D converter (ADC) with proposed area- and power-efficient architecture. The conventional dedicated sample-hold-amplifier (SHA) is eliminated and the matching requirement between the first multiplying digital-to-analog converter (MDAC) and sub-ADC is also avoided by using the SHA merged with the first MDAC (SMDAC) architecture, which features low power and stabilization. Further reduction of power and area is achieved by sharing an opamp between two successive pipelined stages, in which the effect of opamp offset and crosstalk between stages is decreased. So the 10-bit pipelined ADC is realized using just four opamps. The ADC demonstrates a maximum signal-to-noise distortion ratio and spurious free dynamic range of 52.67 dB and 59.44 dB, respectively, with a Nyquist input at full sampling rate. Constant dynamic performance for input frequencies up to 49.7 MHz, which is the twofold Nyquist rate, is achieved at 50 MS/s. The ADC prototype only occupies an active area of 1.81 mm² in a 0.35 μm CMOS process, and consumes 133 mW when sampling at 50 MHz from a 3.3-V power supply.

A 1.8 V 12 bit 100 MS/s pipelined analog to digital converter (ADC) in a 0.18 μm complementary metal--oxide semiconductor process is presented. The first stage adopts a 3.5 bit structure to relax the capacitor matching requirements. A bootstrapped switch and a scaling down technique are used to improve the ADC's linearity and save power dissipation, respectively. With a 15.5 MHz input signal, the ADC achieves 79.8 dB spurious-free dynamic range and 10.5 bit effective number of bits at 100 MS/s. The power consumption is 112 mW at a 1.8 V supply, including output drivers. The chip area is 3.51 mm², including pads.

A CMOS dual-band multi-mode RF front-end for the global navigation satellite system receivers of all GPS, Bei-Dou, Galileo and Glonass systems is presented. It consists of a reconfigurable low noise amplifier (LNA), a broadband active balun, a high linearity mixer and a bandgap reference (BGR) circuit. The effect of the input parasitic capacitance on the input impedance of the inductively degenerated common source LNA is analyzed in detail. By using two different LC networks at the input port and the switched capacitor at the output port, the LNA can work at two different frequency bands (1.2 GHz and 1.5 GHz) under low power consumption. The active balun uses a hybrid-connection structure to achieve high bandwidth. The mixer uses the multiple gated transistors technique to acquire a high linearity under low power consumption but does not deteriorate other performances. The measurement results of the proposed front-end achieve a noise figure of 2.1/2.0 dB, a gain of 33.9/33.8 dB and an input 1-dB compression point of 0/1 dBm at 1227.6/1575.42 MHz. The power consumption is about 16 mW under a 1.8 V power supply.

An integrated fully differential ultra-wideband CMOS RF front-end for 6–9 GHz is presented. A resistive feedback low noise amplifier and a gain controllable IQ merged folded quadrature mixer are integrated as the RF front-end. The ESD protected chip is fabricated in a TSMC 0.13 μm RF CMOS process and achieves a maximum voltage gain of 23–26 dB and a minimum voltage gain of 16–19 dB, an averaged total noise figure of 3.3–4.6 dB while operating in the high gain mode and an in-band IIP3 of –12.6 dBm while in the low gain mode. This RF front-end consumes 17 mA from a 1.2 V supply voltage.

A 264 MHz CMOS 4th G_m–C LPF target for the UWB standard is presented. The filter is designed by cascading two biquad cells. Compared with the previously published biquad cells, the biquad proposed here saves 1 transconductor, 3 CMFB networks and 2 capacitors. Benefiting from these merits, the power consumption and chip area of the 4th order UWB LPF are reduced dramatically without other characteristics being affected. The LPF is designed and fabricated with TSMC 0.18 μm 1P6M CMOS technology. The implemented LPF achieves a power gain of –0.5 dB. The measured frequency response matches well with that of the simulating results. The core chip area is only 0.06 mm², which has a wonderful advantage over those from similar work. The LPF excluding test-buffers dissipates a total current of 3 mA from the 1.8 V power supply.

A novel toggled flip-flop (TFF) divide-by-two circuit (DTC) and its optimization method based on a large-signal analysis approach are proposed. By reducing the output RC constant in tracking mode and making it large in latching mode, compressing the internal signal swing as well as compensating the current leaked in the latching mode, the operating frequency range is greatly expanded. Implemented in a SMIC 0.13 μm RF CMOS process with a 1.2 V power supply, it can work under an ultra-wide frequency band ranging from 320 MHz to 29.6 GHz. Experimental results show that two phase-locked loops (PLLs) with the proposed DTC can achieve in-band phase noise of -94 dBc/Hz @ 10 kHz under 4224 MHz operating frequency and -84 dBc/Hz @ 10 kHz under 10 GHz operating frequency, respectively. The power consumption of the proposed DTC is reduced by almost 50% compared with the conventional counterparts.

The appropriate wet etch process for the selective removal of TaN on the HfSiON dielectric with an amorphous-silicon (a-Si) hardmask is presented. SC1 (NH₄OH : H₂O₂ : H₂O), which can achieve reasonable etch rates for metal gates and very high selectivity to high-k dielectrics and hardmask materials, is chosen as the TaN etchant. Compared with the photoresist mask and the tetraethyl orthosilicate (TEOS) hardmask, the a-Si hardmask is a better choice to achieve selective removal of TaN on the HfSiON dielectric because it is impervious to the SC1 etchant and can be readily etched with NH₄OH solution without attacking the TaN and the HfSiON film. In addition, the surface of the HfSiON dielectric is smooth after the wet etching of the TaN metal gate and a-Si hardmask removal, which could prevent device performance degradation. Therefore, the wet etching of TaN with the a-Si hardmask can be applied to dual metal gate integration for the selective removal of the first TaN metal gate deposition.

The influence of voltage on photo-electrochemical etching (PEC) of macroporous silicon arrays (MSA) was researched. According to the theory of the space charge region, I–V scan curves and the reaction mechanism of the n-type silicon anodic oxidation in HF solution under different current densities, the pore morphology influenced by the working voltage were studied and analyzed in detail. The results show that increasing the etching voltage will lead to distortion of the pore morphology, decreasing etching voltage will result in an increase in the blind porosity, and the constant etching voltage for a long time will cause gradual bifurcation. Through the optimization of the process parameters, the perfect MSA structure with a pore depth of 317 μm, a pore size of 3 μ m and an aspect ratio of 105 was obtained.

The effect of the ammonium molybdate concentration on the material removal rate (MRR) and surface quality in the preliminary chemical mechanical polishing (CMP) of a rough glass substrate was investigated using a silica-based slurry. Experimental results reveal that the ammonium molybdate concentration has a strong influence on the CMP behaviors of glass substrates. When the ammonium molybdate was added to the baseline slurry, polishing rates increased, and then decreased with a transition at 2 wt.%, and the root mean square (RMS) roughness decreased with increasing ammonium molybdate concentration up to 2 wt.%, after which it increased linearly up to 4 wt.%. The improvement in MRR and RMS roughness may be attributed to the complexation of hydrolysis products of the glass substrate with the ammonium molybdate so as to prevent their redeposition onto the substrate surface. It was found that there exists an optimal ammonium molybdate concentration at 2 wt.% for obtaining the highest MRR and the lowest RMS roughness within a particular polishing time.

A novel electroplating indium bumping process is described, as a result of which indium bump arrays with a pitch of 100 μm and a diameter of 40 μm were successfully prepared. UBM (under bump metallization) for indium bumping was investigated with an XRD technique. The experimental results indicate that Ti/Pt (300 Å / 200 Å) has an excellent barrier effect both at room temperature and at 200 ℃. The bonding reliability of the indium bumps was evaluated by a shear test. Results show that the shear strength of the indium bump significantly increases after the first reflow and then changes slowly with increasing reflow times. Such a phenomenon may be caused by the change in textures of the indium after reflow. The corresponding flip-chip process is also discussed in this paper.

In order to understand the fundamentals of the chemical mechanical polishing (CMP) material removal mechanism, the indentation depth of a slurry particle into a wafer surface is determined using the in-situ nanomechanical testing system tribo-indenter by Hysitron. It was found that the removal mechanism in CMP is most probably a molecular scale removal theory. Furthermore, a comprehensive mathematical model was modified and used to pinpoint the effects of wafer/pad relative velocity, which has not been modeled previously. The predicted results based on the current model are shown to be consistent with the published experimental data. Results and analysis may lead to further understanding of the microscopic removal mechanism at the molecular scale in addition to its underlying theoretical foundation.

Nowadays, TFT-LCD manufacturing has become a very complex process, with many different products being manufactured with many different tools. The ability to predict the quality of product in such a high-mix system is critical to developing and maintaining a high yield. In this paper, a statistical method is proposed for building a virtual metrology model from a number of products using a high-mix manufacturing process. Stepwise regression is used to select “key variables" that really affect the quality of the products. Multivariate analysis of covariance is also proposed for simultaneously applying the selected variables and product effect. This framework provides a systematic method of building a processing quality prediction system for a high-mix manufacturing process. The experimental results show that the proposed quality prognostic system can not only estimate the critical dimension accurately but also detect potentially faulty glasses.