Erase voltage impact on 0.18 μm triple self-aligned split-gate flash memory endurance

Dong Yaoqi; Kong Weiran; Nhan Do; Wang Shiuh-Luen; Lee Gabriel

doi:10.1088/1674-4926/31/6/064012

J. Semicond. > 2010, Volume 31 > Issue 6 > 064012

SEMICONDUCTOR DEVICES

Erase voltage impact on 0.18 μm triple self-aligned split-gate flash memory endurance

Dong Yaoqi, Kong Weiran, Nhan Do, Wang Shiuh-Luen and Lee Gabriel

+ Author Affiliations

DOI: 10.1088/1674-4926/31/6/064012

Abstract: The erase voltage impact on the 0.18 μm triple self-aligned split-gate flash endurance is studied. An optimized erase voltage is necessary in order to achieve the best endurance. A lower erase voltage can cause more cell current degradation by increasing its sensitivity to the floating gate voltage drop, which is induced by tunnel oxide charge trapping during program/erase cycling. A higher erase voltage also aggravates the endurance degradation by introducing select gate oxide charge trapping. A progressive erase voltage method is proposed and demonstrated to better balance the two degradation mechanisms and thus further improve endurance performance.

Key words: split-gate flash, endurance, erase voltage

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Dong Yaoqi, Kong Weiran, Nhan Do, Wang Shiuh-Luen, Lee Gabriel. Erase voltage impact on 0.18 μm triple self-aligned split-gate flash memory endurance[J]. Journal of Semiconductors, 2010, 31(6): 064012. doi: 10.1088/1674-4926/31/6/064012

Dong Y Q, Kong W R, N Do, Wang S L, Lee G. Erase voltage impact on 0.18 μm triple self-aligned split-gate flash memory endurance[J]. J. Semicond., 2010, 31(6): 064012. doi: 10.1088/1674-4926/31/6/064012.

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Received: 18 August 2015 Revised: 18 January 2010 Online: Published: 01 June 2010

The erase voltage impact on the 0.18 μm triple self-aligned split-gate flash endurance is studied. An optimized erase voltage is necessary in order to achieve the best endurance. A lower erase voltage can cause more cell current degradation by increasing its sensitivity to the floating gate voltage drop, which is induced by tunnel oxide charge trapping during program/erase cycling. A higher erase voltage also aggravates the endurance degradation by introducing select gate oxide charge trapping. A progressive erase voltage method is proposed and demonstrated to better balance the two degradation mechanisms and thus further improve endurance performance.

Erase voltage impact on 0.18 μm triple self-aligned split-gate flash memory endurance

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Erase voltage impact on 0.18 μm triple self-aligned split-gate flash memory endurance

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