The stability and local vibrational mode (LVM) of hydrogen related p-type AlN have been studied by first-principles calculations based on density functional theory. The stable and metastable microscopic geometries of group-II (Be, Mg, Ca, Sr, Ba)–H complexes have been investigated. The calculated results indicate that BC_|| is the most stable configuration for isolated interstitial H⁺ and Be–H complexes, while it is AB_N,⊥ for Mg–H, Ca–H, Sr–H and Ba–H complexes. Moreover, the vibrational frequencies and the values of k and |α| for the H atom with LVM are calculated. Here, the values of k and |α| are used to describe the parameters of the harmonic and anharmonic contributions, respectively. The calculated results indicate that the larger the size of the doped ion is, the shorter the N–H bond length is, and the larger the potential energy, the vibrational frequencies, the values of k and |α| are. This implies that the size of the doped ion has an important influence on the vibrational properties of H.

Spin-dependent electronic transport through a quantum dot coupled to one ferromagnetic lead and one normal metal lead is investigated by using the master equation approach. Both the intradot spin-flip transition and Coulomb interaction are studied for the current polarization p=(I↑-I↓)/( I↑+I↓). It is found that p is suppressed to zero for a particular regime of one direction bias, while it is enhanced to a relative maximum value when the bias is reversed, which is called the spin-current diode effect. The bias regime of this effect is determined by the dot level position and the intradot Coulomb interaction strength. We give a physical explanation and several control methods for it. This device is realizable with current nanofabrication technology and should have practical applications in spintronics.

In order to fabricate strained-Si MOSFETs, we present a method to prepare strained-Si material with highquality surface and ultra-thin SiGe virtual substrate. By sandwiching a low-temperature Si (LT-Si) layer between a Si buffer and a pseudomorphic Si0.8Ge0.2 layer, the surface roughness root mean square (RMS) is 1.02 nm and the defect density is 1E6 cm-2 owing to the misfit dislocations restricted to the LT-Si layer and the threading dislocations suppressed from penetrating into the Si0.8Ge0.2 layer. By employing PC implantation and rapid thermal annealing, the strain relaxation degree of the Si0.8Ge0.2 layer increases from 85.09% to 96.41% and relaxation is more uniform. Meanwhile, the RMS (1.1 nm) varies a little and the defect density varies little. According to the results, the method of combining an LT-Si layer with ion implantation can prepare high-quality strained-Si material with a high relaxation degree and ultra-thin SiGe virtual substrate to meet the requirements of device applications.

A theoretical compensation method for polygonized mesa structures on (100) silicon substrate during the anisotropic etching process has been developed, which contains four stages as follows: prepare the information of the etching condition; predict the structure’s undercutting profile; construct the topological structure of compensation patterns; and generate practical compensation patterns from the topological structure. The reasoning process is clearly stated, and detailed steps for the undercutting prediction and topological structure construction are summarized. Conclusions are also drawn about the rules which must be obeyed during the pattern generation process. The simulation and experimental results of some polygon structures are finally given to prove this method’s validity and reliability.

Vertically oriented TiO2 nanotube arrays were prepared by potentiostatic anodization of Ti foils in HF/acetic acid (HAC) aqueous solution. Anodization variables including anodization electrolyte concentration, anodization voltage, anodization time and buffer medium can be chosen and adjusted to manipulate the nanotube arrays to give the required length and morphology.

A continuous surface potential versus voltage equation is proposed and then its solution is further discussed for a long channel intrinsic surrounding-gate (SRG) MOSFET from the accumulation to strong inversion region. The original equation is derived from the exact solution of a simplified Poisson equation and then the empirical correction is performed from the mathematical condition required by the continuity of the solution, which results in a continuous surface potential versus voltage equation, allowing the surface potential and the related derivatives to be described by an analytic solution from the accumulation to strong inversion region and from linear to the saturation region accurately and continuously. From these results, the dependences of surface potential and centric potential characteristics on device geometry are analyzed and the results are also verified with the 3-D numerical simulation from the aspect of accuracy and continuity tests.

A new small-signal model for anisomerous AlGaN/GaN high electron mobility transistors (HEMTs) is proposed for accurate prediction of HEMT behavior up to 20 GHz. The parasitic elements are extracted from both cold-FET and pinch-off bias to obtain more precise results and the intrinsic part is directly extracted. All the parameters needed in this process are determined by the device structure rather than optimization methods. This guarantees consistency between the parameter values and the component’s physical meaning.

A process simplification scheme for fabricating CMOS poly-Si thin-film transistors (TFTs) has been proposed, which employs large-angle-tilt-implantation of dopant through a gate sidewall spacer (LATITS). By this LATITS scheme, a lightly doped drain region under the oxide spacer is formed by low-dose tilt implantation of phosphorus (or boron) dopant through the spacer, and then the nC-source/drain (nC-S/D) (or pC-S/D) region is formed via using the same photo-mask layer during CMOS integration. For both n-TFT and p-TFT devices, as compared to the sample with conventional single nC-S/D (or pC-S/D) structure, the LATITS scheme can cause an obviously smaller leakage current, due to more gradual dopant distribution and thus smaller electric field. In addition, the resultant on-state currents only show slight degradation for the LATITS scheme. As a result, by the LATITS scheme, CMOS poly-Si TFT devices with an on/off current ratio well above 8 orders may be achieved without needing extra photo-mask layers during CMOS integration.

A new lateral insulated-gate bipolar transistor (LIGBT) with a SiO2 shielded layer anode on SOI substrate is proposed and discussed. Compared to the conventional LIGBT, the proposed device offers an enhanced conductivity modulation effect due to the SiO2 shielded layer anode structure which can be formed by SIMOX technology. Simulation results show that, for the proposed LIGBT, during the conducting state, the electron–hole plasma concentrations in the n-drift region are several times larger than those of the conventional LIGBT; the conducting current is up to 37% larger than that of the conventional one. The enhanced conductivity modulation effect by SiO2 shielded layer anode does not sacrifice other characteristics of the device, such as breakdown and switching, but is compatible with other optimized technologies.

The optoelectronic properties of heterojunction thin film devices with ITO/CuPc/C60/Al structure have been investigated by analyzing their current–voltage characteristics, optical absorption and photocurrent. In this organic photovoltaic device, CuPc acts as an optically active layer, C60 as an electron-transporting layer and ITO and Al as electrodes. It is observed that, under illumination, excitons are formed, which subsequently drift towards the interface with C60, where an internal electric field is present. The excitons that reach the interface are subsequently dissociated into free charge carriers due to the electric field present at the interface. The experimental results show that in this device the total current density is a function of injected carriers at the electrode–organic semiconductor surface, the leakage current through the organic layer and collected photogenerated current that results from the effective dissociation of excitons.

A novel cascaded DFB laser, which consists of two serial gratings to provide selectable wavelengths, is presented and analyzed by the transfer matrix method. In this method, efficient facet reflectivity is derived from the transfer matrix built for each serial section and is then used to simulate the performance of the novel cascaded DFB laser through self-consistently solving the gain equation, the coupled wave equation and the current continuity equations. The simulations prove the feasibility of this kind of wavelength selectable laser and a corresponding designed device with two selectable wavelengths of 1.51μm and 1.53μm is realized by experiments on InP-based multiple quantum well structure.

A frequency and wavelength tunable self-pulsation laser based on DBR laser devices is reported for the first time. This laser generates continuous tunable optical microwave in the range of 1.87–21.81 GHz with 3-dB linewidth about 10 MHz by tuning the injection currents on the front and back gain sections, and exhibits wavelength tuning range from 1536.28 to 1538.73 nm by tuning the injection currents on the grating section.

This paper reports a new method of fabricating AlGaInP-based nanorod light emitting diodes (LEDs) by using self-assembly metal layer nanomasks and inductively coupled plasma. Light-power measurements indicate that the scattering of photons considerably enhances the probability of escaping from the nanorod LEDs. The light-intensity of the nanorod LED is increased by 34% for a thin GaP window layer, and by 17% for an 8 μm GaP window layer. The light-power of the nanorod LED is increased by 25% and 13%, respectively.

The thermo-optic effect in the lateral-carrier-injection pin junction SOI ridge waveguide is analyzed according to the thermal field equation. Numerical analysis and experimental results show that the thermo-optic effect caused by carrier injection is significant in such devices, especially for small structure ones. For a device with a 1000 μm modulation length, the refractive index rise introduced by heat accounts for 1/8 of the total effect under normal working conditions. A proposal of adjusting the electrode position to cool the devices to diminish the thermal-optic effect is put forward.

Based on thermionic emission theory, a model of a 6H-SiC metal–semiconductor–metal (MSM) ultraviolet photodetector is established with the simulation package ISE-TCAD. A device with 3 μm electrode width (W ) and 3 μm electrode spacing (L) is simulated. The findings show that the MSM photodetector has quite a low dark current of 15 pA at 10 V bias and the photocurrent is two orders of magnitude higher than the dark current. The influences of different structures on dark and illuminated current–voltage characteristics of the MSM photodetector are investigated to optimize the device parameters. Simulation results indicate that the maximum photocurrent and the highest ratio of photocurrent to dark current at 15 V bias are 5.3 nA and 327 with device parameters of W = 6 μm, L = 3 μm and W = 3 μm, L = 6 μm, respectively.

An investigation has been made on the properties of an impedance hygrometer fabricated using cellulose and copper phthalocyanine (Ag/cellulose/CuPc/Ag). A 5wt% suspension of cellulose was prepared in water while the CuPc was dissolved in methanol. Cellulose film was deposited on glass substrates with preliminary deposited metallic electrodes followed by deposition of CuPc film. The resistances and capacitances of the samples were evaluated under the effect of humidity. The impedance was calculated from resistance and capacitance measurements. It was also measured during the experiment. It was observed that the capacitance of the sensor increases and resistance and impedance decrease with an increase in the relative humidity level. It was found that the impedance–humidity relationship showed more uniform changes in the interval of 31%–98% RH than the resistance– and capacitance–humidity relationships that showed visible changes in the humidity intervals of 31%–80% RH and 80%–98% RH respectively. The humiditydependent impedance of the sample makes it attractive for use in impedance hygrometers. The impedance hygrometer may be used in instruments for the environmental monitoring of humidity.

The erase voltage impact on the 0.18 μm triple self-aligned split-gate flash endurance is studied. An optimized erase voltage is necessary in order to achieve the best endurance. A lower erase voltage can cause more cell current degradation by increasing its sensitivity to the floating gate voltage drop, which is induced by tunnel oxide charge trapping during program/erase cycling. A higher erase voltage also aggravates the endurance degradation by introducing select gate oxide charge trapping. A progressive erase voltage method is proposed and demonstrated to better balance the two degradation mechanisms and thus further improve endurance performance.

A fully integrated CMOS phase-locked loop (PLL) which can synthesize a quadrature output frequency of 7.656 GHz is presented. The proposed PLL can be employed as a building block for an MB-OFDM UWB frequency synthesizer. To achieve fast loop settling, integer-N architecture operating with 66 MHz reference frequency and wideband QVCO are implemented. I/Q carriers are generated by two bottom-series cross-coupled LC VCOs. Realized in 0.18 μm CMOS technology, this PLL consumes 16 mA current (including buffers) from a 1.5 V supply and the phase noise is –109.6 dBc/Hz at 1 MHz offset. The measured oscillation frequency shows that the QVCO has a range of 6.95 to 8.73 GHz. The core circuit occupies an area of 1×0.5 mm2.

This paper presents a 10-GHz 8-bit direct digital synthesizer (DDS) microwave monolithic integrated circuit implemented in 1 μm GaAs HBT technology. The DDS takes a double-edge-trigger (DET) 8-stage pipeline accumulator with sine-weighted DAC-based ROM-less architecture, which can maximize the utilization ratio of the GaAs HBT’s high-speed potential. With an output frequency up to 5 GHz, the DDS gives an average spurious free dynamic range of 23.24 dBc through the first Nyquist band, and consumes 2.4 W of DC power from a single –4.6 V DC supply. Using 1651 GaAs HBT transistors, the total area of the DDS chip is 2.4×2.0 mm2.

A frequency synthesizer for the ultra-wide band (UWB) group #1 is proposed. The synthesizer uses a phaselocked loop (PLL) and single-sideband (SSB) mixers to generate the three center frequencies of the first band group by mixing 4224 MHz with 264 MHz and 792 MHz, respectively. A novel multi-QSSB mixer is designed to combine the function of frequency selection and frequency conversion for low power and high linearity. The synthesizer is fabricated in Jazz 0.18-μm RF CMOS technology. The measured reference spur is as low as –69 dBc and the maximum spur is the LO leakage of –32 dBc. A low phase noise of –110 dBc/Hz @ 1 MHz offset and an integrated phase noise of 1.86 are achieved. The hopping time between different bands is less than 1.8 ns. The synthesizer consumes 30 mA from a 1.8 V supply.

A power efficient 8-bit successive approximation register (SAR) A/D for the vital sign monitoring of a wireless body sensor network (WBSN) is presented. A charge redistribution architecture is employed. The prototype A/D is fabricated in 0.18 μm CMOS. The A/D achieves 7.5ENOB with sampling rate varying from 64 kHz to 1.5 MHz. The power consumption varies from 10.8 to 225.7 W.

This paper describes a novel low-power wideband low-phase noise divide-by-two frequency divider. Hereby, a new D-latch topology is introduced. By means of conventional dynamic source-coupled logic techniques, the divider demonstrates a wideband with low phase noise by adding a switch transistor between the clock port and the couple node of the input NMOS pair in the D latch. The chip was fabricated in the 90-nm CMOS process of IBM. The measurement results show that the frequency divider has an input frequency range from 0.05 to 10 GHz and the phase noise is –159.8 dBc/Hz at 1 MHz offset from the carrier. Working at 10 GHz, the frequency divider dissipates a total power of 9.12 mW from a 1.2 V supply while occupying only 0.008 mm2 of the core die area.

This paper presents a current-mode voltage regulator for a passive UHF RFID transponder. The passive tag power is extracted from RF energy through the RF-to-DC rectifier. Due to huge variations of the incoming RF power, the rectifier output voltage should be regulated to achieve a stable power supply. By accurately controlling the current flowing into the load with an embedded sub-threshold reference, the regulated voltage varies in a range of 1–1.3 V from –20 to 80 ℃, and a bandwidth of about 100 kHz is achieved for a fast power recovery. The circuit is fabricated in UMC 0.18 μm mixed-mode CMOS technology, and the current consumption is only 1 μA.

A monolithic RF transceiver for an MB-OFDM UWB system in 3.1–4.8 GHz is presented. The transceiver adopts direct-conversion architecture and integrates all building blocks including a gain controllable wideband LNA, a I/Q merged quadrature mixer, a fifth-order Gm–C bi-quad Chebyshev LPF/VGA, a fast-settling frequency synthesizer with a poly-phase filter, a linear broadband up-conversion quadrature modulator, an active D2S converter and a variablegain power amplifier. The ESD protected transceiver is fabricated in Jazz Semiconductor’s 0.18-μm RF CMOS with an area of 6.1 mm2 and draws a total current of 221 mA from 1.8-V supply. The receiver achieves a maximum voltage gain of 68 dB with a control range of 42 dB in 6 dB/step, noise figures of 5.5–8.8 dB for three sub-bands, and an inband/out-band IIP3 better than -4 dBm/+9 dBm. The transmitter achieves an output power ranging from -10.7 to -3 dBm with gain control, an output P1dB better than -7.7 dBm, a sideband rejection about 32.4 dBc, and LO suppression of 31.1 dBc. The hopping time among sub-bands is less than 2.05 ns.

A sixth-order Butterworth Gm-C low-pass filter (LPF) with a continuous tuning architecture has been implemented for a wireless LAN (WLAN) transceiver in 0.35 μm CMOS technology. An interior node scaling technique has been applied directly to the LPF to improve the dynamic range and the structure of the LPF has been optimized to reduce both the die size and the current consumption. Measurement results show that the filter has 77.5 dB dynamic range, 16.3 ns group delay variation, better than 3% cutoff frequency accuracy, and 0 dBm passband IIP3. The whole LPF with the tuning circuit dissipates only 1.42 mA (5 MHz cutoff frequency) or 2.81 mA (10 MHz cutoff frequency) from 2.85 V supply voltage, and only occupies 0.175 mm2 die size.

A rotary traveling-wave oscillator (RTWO) targeted at 5.8 GHz band operation is designed and fabricated using standard 0.18 μm CMOS technology. Both simulation and measurement results are presented. The chip size including pads is 1.5×1.5 mm2. The measured output power at a frequency of 5.285 GHz is 6.68 dBm, with a phase noise of –102 dBc/Hz at 1 MHz offset from the carrier.

A novel monolithic digitalized random carrier frequency modulation spread-spectrum clock generator (RCF-SSCG) is proposed. In this design, the output frequency of the proposed RCF-SSCG changes with the intensity of the capacitive charge and discharge current. Its analytical model is induced and the effect of the modulation parameters on the spread spectrum is numerically simulated and discussed. Compared with other works, this design has the advantages of small size, low power consumption and good robustness. The circuit has been fabricated in a 0.5 μm CMOS process and applied to a class D amplifier in which the proposed RCF-SSCG occupies an area of 0.112 mm2 and consumes 9 mW. The experimental results confirm the theoretical analyses.

In this paper, An improved adaptive frequency calibration (AFC) has been employed to implement a fast lock phase-locked loop (PLL)-based frequency synthesizer in a 0.18 μm CMOS process. The AFC can work in two modes: the frequency calibration mode and the store/load mode. In the frequency calibration mode, a novel frequency-detector is used to reduce the frequency calibration time to 16 μs typically. In the store/load mode, the AFC makes voltage-controlled oscillator (VCO) return to the calibrated frequency in about 1 μs through loading the calibration result stored after the frequency calibration. The experimental results show that the VCO tuning frequency range is about 620~920 MHz and the in-band phase noise within the loop bandwidth of 10 kHz is -82 dBc/Hz. The lock time is about 20 μs in frequency calibration mode and about 5 μs in store/load mode. The synthesizer consumes 12 mA from a single 1.8 V supply voltage when steady.

A low-power frequency synthesizer for GPS/Galileo L1/E1 band receivers implemented in a 0.18 μm CMOS process is introduced. By adding clock-controlled transistors at latch outputs to reduce the time constant at sensing time, the working frequency of the high-speed source-coupled logic prescaler supplying quadrature local oscillator signals has been increased, compared with traditional prescalers. Measurement results show that this synthesizer achieves an in-band phase noise of –87 dBc/Hz at 15 kHz offset, with spurs less than –65 dBc. The whole synthesizer consumes 6 mA in the case of a 1.8 V supply, and its core area is 0.6 mm2.

This paper presents a 1 kb sub-threshold SRAM in the 180 nm CMOS process based on an improved 11T SRAM cell with new structure. Final test results verify the function of the SRAM. The minimal operating voltage of the chip is 350 mV, where the speed is 165 kHz, the leakage power is 42 nW and the dynamic power is about 200 nW. The designed SRAM can be used in ultra-low-power SoC.

A fast automatic power control (APC) circuit for a laser diode driver (LDD) has been implemented in a 0.6-μm BiCMOS process. The APC circuit adopts double-loops and variable-bandwidth techniques to achieve a turnon time of < 400 μs for most kinds of TOSAs. Thus, it meets the small form-factor pluggable (SFP) agreement. Such techniques make a good tradeoff between stability, accuracy, turn-on time, noise and convenience. The measured results indicate that the APC circuit is suitable for SFP LDD.

A 1.4-V 8-bit 300-MS/s folding and interpolating analog-to-digital converter (ADC) is proposed. Fabricated in the 0.13-μm CMOS process and occupying only 0.6-mm2 active area, the ADC is especially suitable for embedded applications. The system is optimized for a low-power purpose. Pipelining sampling switches help to cut down the extra power needed for complete settling. An averaging resistor array is placed between two folding stages for power-saving considerations. The converter achieves 43.4-dB signal-to-noise and distortion ratio and 53.3-dB spurious-free dynamic range at 1-MHz input and 42.1-dB and 49.5-dB for Nyquist input. Measured results show a power dissipation of 34 mW and a figure of merit of 1.14 pJ/convstep at 250-MHz sampling rate at 1.4-V supply.

This paper presents a novel temperature independent current reference based on the theory of mutual compensation of mobility and threshold voltage. It is completely compatible with standard CMOS-technology. The experiment results indicate that the temperature coefficient of this current reference is less than 290 ppm/ C over a temperature range from –20 to 110 ℃.