SEMICONDUCTOR INTEGRATED CIRCUITS
Abstract: In this paper, An improved adaptive frequency calibration (AFC) has been employed to implement a fast lock phase-locked loop (PLL)-based frequency synthesizer in a 0.18 μm CMOS process. The AFC can work in two modes: the frequency calibration mode and the store/load mode. In the frequency calibration mode, a novel frequency-detector is used to reduce the frequency calibration time to 16 μs typically. In the store/load mode, the AFC makes voltage-controlled oscillator (VCO) return to the calibrated frequency in about 1 μs through loading the calibration result stored after the frequency calibration. The experimental results show that the VCO tuning frequency range is about 620~920 MHz and the in-band phase noise within the loop bandwidth of 10 kHz is -82 dBc/Hz. The lock time is about 20 μs in frequency calibration mode and about 5 μs in store/load mode. The synthesizer consumes 12 mA from a single 1.8 V supply voltage when steady.
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Received: 18 August 2015 Revised: 18 January 2010 Online: Published: 01 June 2010
| Citation: |
Yin Yadong, Yan Yuepeng, Liang Weiwei, Du Zhankun. A fast lock frequency synthesizer using an improved adaptive frequency calibration[J]. Journal of Semiconductors, 2010, 31(6): 065011. doi: 10.1088/1674-4926/31/6/065011
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Yin Y D, Yan Y P, Liang W W, Du Z K. A fast lock frequency synthesizer using an improved adaptive frequency calibration[J]. J. Semicond., 2010, 31(6): 065011. doi: 10.1088/1674-4926/31/6/065011.
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