SEMICONDUCTOR INTEGRATED CIRCUITS
Yu Yunfeng, Yue Jianlian, Xiao Shimao, Zhuang Haixiao, Ma Chengyan and Ye Tianchun
Abstract: A low-power frequency synthesizer for GPS/Galileo L1/E1 band receivers implemented in a 0.18 μm CMOS process is introduced. By adding clock-controlled transistors at latch outputs to reduce the time constant at sensing time, the working frequency of the high-speed source-coupled logic prescaler supplying quadrature local oscillator signals has been increased, compared with traditional prescalers. Measurement results show that this synthesizer achieves an in-band phase noise of –87 dBc/Hz at 15 kHz offset, with spurs less than –65 dBc. The whole synthesizer consumes 6 mA in the case of a 1.8 V supply, and its core area is 0.6 mm2.
Key words: frequency synthesizer, GPS, CMOS, PLL, source-coupled logic, prescaler
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Received: 18 August 2015 Revised: 27 January 2010 Online: Published: 01 June 2010
| Citation: |
Yu Yunfeng, Yue Jianlian, Xiao Shimao, Zhuang Haixiao, Ma Chengyan, Ye Tianchun. A low-power CMOS frequency synthesizer for GPS receivers[J]. Journal of Semiconductors, 2010, 31(6): 065012. doi: 10.1088/1674-4926/31/6/065012
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Yu Y F, Yue J L, Xiao S M, Zhuang H X, Ma C Y, Ye T C. A low-power CMOS frequency synthesizer for GPS receivers[J]. J. Semicond., 2010, 31(6): 065012. doi: 10.1088/1674-4926/31/6/065012.
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