An ultra-low-power 1 kb sub-threshold SRAM in the 180 nm CMOS process

Liu Ming; Chen Hong; Li Changmeng; Wang Zhihua

doi:10.1088/1674-4926/31/6/065013

J. Semicond. > 2010, Volume 31 > Issue 6 > 065013

SEMICONDUCTOR INTEGRATED CIRCUITS

An ultra-low-power 1 kb sub-threshold SRAM in the 180 nm CMOS process

Liu Ming, Chen Hong, Li Changmeng and Wang Zhihua

+ Author Affiliations

DOI: 10.1088/1674-4926/31/6/065013

Abstract: This paper presents a 1 kb sub-threshold SRAM in the 180 nm CMOS process based on an improved 11T SRAM cell with new structure. Final test results verify the function of the SRAM. The minimal operating voltage of the chip is 350 mV, where the speed is 165 kHz, the leakage power is 42 nW and the dynamic power is about 200 nW. The designed SRAM can be used in ultra-low-power SoC.

Key words: sub-threshold SRAM

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Received: 18 August 2015 Revised: 05 February 2010 Online: Published: 01 June 2010

This paper presents a 1 kb sub-threshold SRAM in the 180 nm CMOS process based on an improved 11T SRAM cell with new structure. Final test results verify the function of the SRAM. The minimal operating voltage of the chip is 350 mV, where the speed is 165 kHz, the leakage power is 42 nW and the dynamic power is about 200 nW. The designed SRAM can be used in ultra-low-power SoC.

An ultra-low-power 1 kb sub-threshold SRAM in the 180 nm CMOS process

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An ultra-low-power 1 kb sub-threshold SRAM in the 180 nm CMOS process

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An ultra-low-power 1 kb sub-threshold SRAM in the 180 nm CMOS process

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