An ultra-low-power 1 kb sub-threshold SRAM in the 180 nm CMOS process

Liu Ming; Chen Hong; Li Changmeng; Wang Zhihua

doi:10.1088/1674-4926/31/6/065013

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Liu Ming, Chen Hong, Li Changmeng, Wang Zhihua. An ultra-low-power 1 kb sub-threshold SRAM in the 180 nm CMOS process[J]. Journal of Semiconductors, 2010, 31(6): 065013. doi: 10.1088/1674-4926/31/6/065013 ****Liu M, Chen H, Li C M, Wang Z H. An ultra-low-power 1 kb sub-threshold SRAM in the 180 nm CMOS process[J]. J. Semicond., 2010, 31(6): 065013. doi: 10.1088/1674-4926/31/6/065013.

Citation:

Liu Ming, Chen Hong, Li Changmeng, Wang Zhihua. An ultra-low-power 1 kb sub-threshold SRAM in the 180 nm CMOS process[J]. Journal of Semiconductors, 2010, 31(6): 065013. doi: 10.1088/1674-4926/31/6/065013 ****

Liu M, Chen H, Li C M, Wang Z H. An ultra-low-power 1 kb sub-threshold SRAM in the 180 nm CMOS process[J]. J. Semicond., 2010, 31(6): 065013. doi: 10.1088/1674-4926/31/6/065013.

Citation:

Liu M, Chen H, Li C M, Wang Z H. An ultra-low-power 1 kb sub-threshold SRAM in the 180 nm CMOS process[J]. J. Semicond., 2010, 31(6): 065013. doi: 10.1088/1674-4926/31/6/065013.

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An ultra-low-power 1 kb sub-threshold SRAM in the 180 nm CMOS process

doi: 10.1088/1674-4926/31/6/065013

Tsinghua National Laboratory for Information Science and Technology, Institute of Microelectronics, Tsinghua University, Beijing 100084, China
Tsinghua National Laboratory for Information Science and Technology, Institute of Microelectronics, Tsinghua University, Beijing 100084, China
Tsinghua National Laboratory for Information Science and Technology, Institute of Microelectronics, Tsinghua University, Beijing 100084, China
Tsinghua National Laboratory for Information Science and Technology, Institute of Microelectronics, Tsinghua University, Beijing 100084, China

Received Date: 2015-08-18
Accepted Date: 2009-11-16
Revised Date: 2010-02-05
Published Date: 2010-06-03

Abstract

Abstract

This paper presents a 1 kb sub-threshold SRAM in the 180 nm CMOS process based on an improved 11T SRAM cell with new structure. Final test results verify the function of the SRAM. The minimal operating voltage of the chip is 350 mV, where the speed is 165 kHz, the leakage power is 42 nW and the dynamic power is about 200 nW. The designed SRAM can be used in ultra-low-power SoC.
- sub-threshold SRAM

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An ultra-low-power 1 kb sub-threshold SRAM in the 180 nm CMOS process

doi: 10.1088/1674-4926/31/6/065013

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An ultra-low-power 1 kb sub-threshold SRAM in the 180 nm CMOS process

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