A low power 12-bit 30 MSPS CMOS pipeline ADC with on-chip voltage reference buffer

Chen Qihui; Qin Yajie; Lu Bo; Hong Zhiliang

doi:10.1088/1674-4926/32/1/015003

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Chen Qihui, Qin Yajie, Lu Bo, Hong Zhiliang. A low power 12-bit 30 MSPS CMOS pipeline ADC with on-chip voltage reference buffer[J]. Journal of Semiconductors, 2011, 32(1): 015003. doi: 10.1088/1674-4926/32/1/015003 ****Chen Q H, Qin Y J, Lu B, Hong Z L. A low power 12-bit 30 MSPS CMOS pipeline ADC with on-chip voltage reference buffer[J]. J. Semicond., 2011, 32(1): 015003. doi: 10.1088/1674-4926/32/1/015003.

Citation:

Chen Qihui, Qin Yajie, Lu Bo, Hong Zhiliang. A low power 12-bit 30 MSPS CMOS pipeline ADC with on-chip voltage reference buffer[J]. Journal of Semiconductors, 2011, 32(1): 015003. doi: 10.1088/1674-4926/32/1/015003 ****

Chen Q H, Qin Y J, Lu B, Hong Z L. A low power 12-bit 30 MSPS CMOS pipeline ADC with on-chip voltage reference buffer[J]. J. Semicond., 2011, 32(1): 015003. doi: 10.1088/1674-4926/32/1/015003.

Citation:

Chen Q H, Qin Y J, Lu B, Hong Z L. A low power 12-bit 30 MSPS CMOS pipeline ADC with on-chip voltage reference buffer[J]. J. Semicond., 2011, 32(1): 015003. doi: 10.1088/1674-4926/32/1/015003.

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A low power 12-bit 30 MSPS CMOS pipeline ADC with on-chip voltage reference buffer

DOI: 10.1088/1674-4926/32/1/015003

State Key Laboratory of ASIC and System, Fudan University, Shanghai 201203, China
State Key Laboratory of ASIC and System, Fudan University, Shanghai 201203, China
State Key Laboratory of ASIC and System, Fudan University, Shanghai 201203, China
State Key Laboratory of ASIC and System, Fudan University, Shanghai 201203, China

Received Date: 2015-08-18
Accepted Date: 2010-07-12
Revised Date: 2010-09-11
Published Date: 2010-12-19

Abstract

Abstract

A 12-bit 30 MSPS pipeline analog-to-digital converter (ADC) implemented in 0.13-μm 1P8M CMOS technology is presented. Low power design with the front-end sample-and-hold amplifier removed is proposed. Except for the first stage, two-stage cascode-compensated operational amplifiers with dual inputs are shared between successive stages to further reduce power consumption. The ADC presents 65.3 dB SNR, 75.8 dB SFDR and 64.6 dB SNDR at 5 MHz analog input with 30.7 MHz sampling rate. The chip dissipates 33.6 mW from 1.2 V power supply. FOM is 0.79 pJ/conv step.
- analog-to-digital converter,
- pipeline,
- SHA removing,
- opamp,
- on-chip reference buffer

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A low power 12-bit 30 MSPS CMOS pipeline ADC with on-chip voltage reference buffer

DOI: 10.1088/1674-4926/32/1/015003

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A low power 12-bit 30 MSPS CMOS pipeline ADC with on-chip voltage reference buffer

DOI: 10.1088/1674-4926/32/1/015003

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