J. Semicond. > 2011, Volume 32 > Issue 11 > 114002
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SEMICONDUCTOR DEVICES

Design of 700 V triple RESURF nLDMOS with low on-resistance

Yin Shan, Qiao Ming, Zhang Yongman and Zhang Bo

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DOI: 10.1088/1674-4926/32/11/114002

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Abstract: A 700 V triple RESURF nLDMOS with a low specific on-resistance of 100 mΩ·cm2 is designed. Compared with a conventional double RESURF nLDMOS whose P-type layer is located on the surface of the drift region, the P-type layer of a triple RESURF nLDMOS is located within it. The difference between the locations of the P-type layer means that a triple RESURF nLDMOS has about a 30% lower specific on-resistance at the same given breakdown voltage of 700 V. Detailed research of the influences of various parameters on breakdown voltage, specific on-resistance, as well as process tolerance is involved. The results may provide guiding principles for the design of triple RESURF nLDMOS.

Key words: nLDMOS, triple RESURF, breakdown voltage, specific on-resistance, charge sharing

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    Received: 03 December 2014 Revised: 05 July 2011 Online: Published: 01 November 2011

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      Article Navigation >  Journal of Semiconductors  > 2011  >  32(11): 114002
      Yin Shan, Qiao Ming, Zhang Yongman, Zhang Bo. Design of 700 V triple RESURF nLDMOS with low on-resistance[J]. Journal of Semiconductors, 2011, 32(11): 114002. doi: 10.1088/1674-4926/32/11/114002 ****Yin S, Qiao M, Zhang Y M, Zhang B. Design of 700 V triple RESURF nLDMOS with low on-resistance[J]. J. Semicond., 2011, 32(11): 114002. doi: 10.1088/1674-4926/32/11/114002.
      Citation:
      Yin Shan, Qiao Ming, Zhang Yongman, Zhang Bo. Design of 700 V triple RESURF nLDMOS with low on-resistance[J]. Journal of Semiconductors, 2011, 32(11): 114002. doi: 10.1088/1674-4926/32/11/114002 ****
      Yin S, Qiao M, Zhang Y M, Zhang B. Design of 700 V triple RESURF nLDMOS with low on-resistance[J]. J. Semicond., 2011, 32(11): 114002. doi: 10.1088/1674-4926/32/11/114002.
      shu

      Design of 700 V triple RESURF nLDMOS with low on-resistance

      DOI: 10.1088/1674-4926/32/11/114002

      • State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China

      • School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore, 639798, Singapore

      • State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China

      • State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China

      • State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China

      Funds:

      The National Natural Science Foundation of China (General Program, Key Program, Major Research Plan)

      • Received Date: 2014-12-03
      • Accepted Date: 2011-03-02
      • Revised Date: 2011-07-05
      • Published Date: 2011-10-20

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