Novel SEU hardened PD SOI SRAM cell

Xie Chengmin; Wang Zhongfang; Wang Xihu; Wu Longsheng; Liu Youbao

doi:10.1088/1674-4926/32/11/115017

J. Semicond. > 2011, Volume 32 > Issue 11 > 115017

SEMICONDUCTOR INTEGRATED CIRCUITS

Novel SEU hardened PD SOI SRAM cell

Xie Chengmin, Wang Zhongfang, Wang Xihu, Wu Longsheng and Liu Youbao

+ Author Affiliations

DOI: 10.1088/1674-4926/32/11/115017

Abstract: A novel SEU hardened 10T PD SOI SRAM cell is proposed. By dividing each pull-up and pull-down transistor in the cross-coupled inverters into two cascaded transistors, this cell suppresses the parasitic BJT and source-drain penetration charge collection effect in PD SOI transistor which causes the SEU in PD SOI SRAM. Mixed-mode simulation shows that this novel cell completely solves the SEU, where the ion affects the single transistor. Through analysis of the upset mechanism of this novel cell, SEU performance is roughly equal to the multiple-cell upset performance of a normal 6T SOI SRAM and it is thought that the SEU performance is 17 times greater than traditional 6T SRAM in 45nm PD SOI technology node based on the tested data of the references. To achieve this, the new cell adds four transistors and has a 43.4% area overhead and performance penalty.

Key words: SEU

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Received: 20 August 2015 Revised: 11 June 2011 Online: Published: 01 November 2011

A novel SEU hardened 10T PD SOI SRAM cell is proposed. By dividing each pull-up and pull-down transistor in the cross-coupled inverters into two cascaded transistors, this cell suppresses the parasitic BJT and source-drain penetration charge collection effect in PD SOI transistor which causes the SEU in PD SOI SRAM. Mixed-mode simulation shows that this novel cell completely solves the SEU, where the ion affects the single transistor. Through analysis of the upset mechanism of this novel cell, SEU performance is roughly equal to the multiple-cell upset performance of a normal 6T SOI SRAM and it is thought that the SEU performance is 17 times greater than traditional 6T SRAM in 45nm PD SOI technology node based on the tested data of the references. To achieve this, the new cell adds four transistors and has a 43.4% area overhead and performance penalty.

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