SEMICONDUCTOR INTEGRATED CIRCUITS
Xu Hua, Wang Lei, Shi Yin and Dai Fa Foster
Abstract: A 2.4 GHz low-power, low-noise and highly linear receiver front-end with a low noise amplifier (LNA) and balun optimization is presented. Direct conversion architecture is employed for this front-end. The on-chip balun is designed for single-to-differential conversion between the LNA and the down-conversion mixer, and is optimized for the best noise performance of the front-end. The circuit is implemented with 0.35 μm SiGe BiCMOS technology. The front-end has three gain steps for maximization of the input dynamic range. The overall maximum gain is about 36 dB. The double-sideband noise figure is 3.8 dB in high gain mode and the input referred third-order intercept point is 12.5 dBm in low gain mode. The down-conversion mixer has a tunable parallel R-C load at the output and an emitter follower is used as the output stage for testing purposes. The total front-end dissipation is 33 mW under a 2.85 V supply and occupies a 0.66 mm2 die size.
Key words: front-end, LNA, balun, mixer, direct-conversion
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Received: 20 August 2015 Revised: 25 April 2011 Online: Published: 01 September 2011
| Citation: |
Xu Hua, Wang Lei, Shi Yin, Dai Fa Foster. Design and optimization of a 2.4 GHz RF front-end with an on-chip balun[J]. Journal of Semiconductors, 2011, 32(9): 095004. doi: 10.1088/1674-4926/32/9/095004
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Xu H, Wang L, Shi Y, Dai F F. Design and optimization of a 2.4 GHz RF front-end with an on-chip balun[J]. J. Semicond., 2011, 32(9): 095004. doi: 10.1088/1674-4926/32/9/095004.
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