The protons in the secondary beam in the Beijing Electron Positron Collider (BEPC) are first analyzed and a large proportion at the energy of 50-100 MeV supply a source gap of high energy protons. In this study, the proton energy spectrum of the secondary beam was obtained and a model for calculating the proton single event upset (SEU) cross section of a static random access memory (SRAM) cell has been presented in the BEPC secondary beam proton radiation environment. The proton SEU cross section for different characteristic dimensions has been calculated. The test of SRAM SEU cross sections has been designed, and a good linear relation between SEUs in SRAM and the fluence was found, which is evidence that an SEU has taken place in the SRAM. The SEU cross sections were measured in SRAM with different dimensions. The test result shows that the SEU cross section per bit will decrease with the decrease of the characteristic dimensions of the device, while the total SEU cross section still increases upon the increase of device capacity. The test data accords with the calculation results, so the high-energy proton SEU test on the proton beam in the BEPC secondary beam could be conducted.

The electronic and transport properties of embedded boron nitride (BN) nanodot superlattices of armchair graphene nanoribbons are studied by first-principles calculations. The band structure of the graphene superlattice strongly depends on the geometric shape and size of the BN nanodot, as well as the concentration of nanodots. The conduction bands and valence bands near the Fermi level are nearly symmetric, which is induced by electron-hole symmetry. When B and N atoms in the graphene superlattices with a triangular BN nanodot are exchanged, the valance bands and conduction bands are inverted with respect to the Fermi level due to electron-hole symmetry. In addition, the hybridization of π orbitals from C and redundant B atoms or N atoms leads to a localized band appearing near the Fermi level. Our results also show a series of resonant peaks appearing in the conductance. This strongly depends on the distance of the two BN nanodots and on the shape of the BN nanodot. Controlling these parameters might allow the modulation of the electronic response of the systems.

Slag refining, as an important option for boron removal to produce solar grade silicon (SOG-Si) from metallurgical grade silicon (MG-Si), has attracted increasing attention. In this paper, Na₂CO₃-SiO₂ systems were chosen as the sodium-based refining slag materials for boron removal from molten silicon. Furthermore, the effect of Al₂O₃ addition for boron removal was studied in detail, which showed that an appropriate amount of Al₂O₃ can help retention of the basicity of the slags, hence improving the boron removal rate.

A new technique to generate a millimeter (mm)-wave carrier of 32.57 GHz (f_LO = 10.85 GHz) with single sideband modulation (SSB) for radio-over-fiber (RoF) systems is experimentally demonstrated by using stimulated Brillouin scattering (SBS). The SSB is realized by directly amplifying the +3rd sideband of the modulated optical carrier in the process of SBS. The pump wave is provided through a double Brillouin scattering frequency shifting configuration. The use of the same laser source to generate the pump wave ensures the stability of the mm-wave generation system since the relative frequency shift between them can be eliminated. In addition, the mm-wave carrier obtains an RF power gain of 21 dB with the SBS amplification and a 3-dB bandwidth of 10 kHz.

A simple and easy hydrothermal process has been employed to synthesize flower-like ZnO products consisting of numerous orderly oriented and bundled nanorods. The structure and morphology of the novel ZnO structure are characterized in detail. The flower-like ZnO-nanorod-based gas sensors are investigated for their ethanol-sensing properties, and the results reveal that the sensors exhibit a high response of 143.6 to 1000 ppm ethanol and good selectivity at the optimal operating temperature of 250 ℃. The effect of the flower-like morphology on the response of the gas sensors to ethanol is also investigated.

InAlN epilayers were grown on high quality GaN and AlN templates with the same growth parameters. Measurement results showed that two samples had the same In content of ~16%, while the crystal quality and surface topography of the InAlN epilayer grown on the AlN template, with 282.3″ (002) full width at half maximum (FWHM) of rocking curve, 313.5″ (102) FWHM, surface roughness of 0.39 nm and V-pit density of 2.8 × 10⁸ cm^-2, were better than that of the InAlN epilayer grown on the GaN template, 309.3″, 339.1″, 0.593 nm and 4.2 × 10⁸ cm^-2. A primary conclusion was proposed that both the crystal quality and the surface topography of the InAlN epilayer grown on the AlN template were better than that of the InAlN epilayer grown on the GaN template. Therefore, the AlN template was a better choice than the GaN template for getting high quality InAlN epilayers.

Comparisons are performed to study the drive current of accumulation-mode (AM) p-channel wrap-gated Fin-FETs. The drive current of the AM p-channel FET is 15%-26% larger than that of the inversion-mode (IM) p-channel FET with the same wrap-gated fin channel, because of the body current component in the AM FET, which becomes less dominative as the gate overdrive becomes larger. The drive currents of the AM p-channel wrap-gated Fin-FETs are 50% larger than those of the AM p-channel planar FETs, which arises from effective conducting surface broadening and volume accumulation in the AM wrap-gated Fin-FETs. The effective conducting surface broadening is due to wrap-gate-induced multi-surface conduction, while the volume accumulation, namely the majority carrier concentration anywhere in the fin cross section exceeding the fin doping density, is due to the coupling of electric fields from different parts of the wrap gate. Moreover, for AM p-channel wrap-gated Fin-FETs, the current in channel along <110> is larger than that in channel along <100>, which arises from the surface mobility difference due to different transport directions and surface orientations. That is more obvious as the gate overdrive becomes larger, when the surface current component plays a more dominative role in the total current.

Criterion for the second snapback of an LDMOS with an embedded SCR is given based on parasitic parameter analysis. According to this criterion, three typical structures are compared by numerical simulation and structural parameters which influence the second snapback are also analyzed to optimize the ESD characteristics. Experimental data showed that, as the second snapback voltage decreased from 25.4 to 8.1 V, the discharge ability of the optimized structure increased from 0.57 to 3.1 A.

This paper presents a 3.4-3.6 GHz power amplifier (PA) designed and implemented in InGaP/GaAs HBT technology. By optimizing the off-chip output matching network and designing an extra input-matching circuit on the PCB, several problems are resolved, such as resonant frequency point migration, worse matching and lower gain caused by parasitics inside and outside of the chip. Under V_cc = 4.3 V and V_bias = 3.3 V, a P_1dB of 27.1 dBm has been measured at 3.4 GHz with a PAE of 25.8%, the 2nd and 3rd harmonics are -64 dBc and -51 dBc, respectively. In addition, this PA shows a linear gain more than 28 dB with S₁₁ < -12.4 dB and S₂₂ < -7.4 dB in 3.4-3.6 GHz band.

H₅ photonic crystal (PC) microcavities co-implanted with erbium (Er) and oxygen (O) ions were fabricated on silicon-on-insulator (SOI) wafers. Photoluminescence (PL) measurements were taken at room temperature and a light extraction enhancement of up to 12 was obtained at 1.54 μm, as compared to an identically implanted unpatterned SOI wafer. In addition, we also explored the adjustment of cavity modes by changing the structural parameters of the PC, and the measured results showed that the cavity-resonant peaks shifted towards shorter wavelengths as the radius of the air holes increased, which is consistent with the theoretical simulation.

We have investigated the properties of C60-based organic field effect transistors (OFETs) with a tris(8-hydroxyquinoline) aluminum (Alq3) buffer layer inserted between the source/drain electrodes and the active material. The electrical characteristics of OFETs are improved with the insertion of Alq3 film. The peak field effect mobility is increased to 1.28 × 10^-2 cm²/(V.s) and the threshold voltage is decreased to 10 V when the thickness of the Alq3 is 10 nm. The reason for the improved performance of the devices is probably due to the prevention of metal atoms diffusing into the C60 active layer and the reduction of the channel resistance in Alq3 films.

A semiconductor laser diode stack is used for pumping and 8 semiconductor laser diode arrays of the stack are put on a sphere, and the output of every bar is specially off-axis compressed to realize high coupling efficiency. The output beam of this semiconductor laser diode stack is shaped by a hollow duct to the laser active medium. The efficiency of the hollow light pipe, which is used for semiconductor laser diode stack coupling, is analyzed by geometric optics and ray tracing. Geometric optics analysis diagnoses the reasons for coupling loss and guides the design of the structure. Ray tracing analyzes the relation between the structural parameters and the output characteristics of this pumping system, and guides parameter optimization. Simulation and analysis results show that putting the semiconductor laser diode arrays on a spherical surface can increase coupling efficiency, reduce the optimum duct length and improve the output energy field distribution.

Pb(Zr_0.52Ti_0.48)O₃ (PZT) thin films have been deposited on a p-type Si substrate separated by a polycrystalline silicon/SiO₂ stacked buffer layer. The X-ray diffraction peaks of the PZT thin films prepared on the polycrystalline silicon annealed at different temperatures were measured. In addition, the polarization of the Pt/PZT/polycrystalline silicon capacitor has been investigated. The memory capacitor of the metal/ferroelectric/polycrystalline silicon/SiO₂/semiconductor structure annealed at 650 ℃ exhibits a clockwise capacitance-voltage hysteresis loop due to the ferroelectric polarization of the PZT thin film. The memory window increases with increasing the area coupling ratio between the SiO₂ capacitor and the PZT capacitor.

In the case of N-type solar cells, the anti-reflection property, as one of the important factors to further improve the energy-conversion efficiency, has been optimized using a stacked Al₂O₃/SiN_x layer. The effect of SiN_x layer thickness on the surface reflection property was systematically studied in terms of both experimental and theoretical measurement. In the stacked Al₂O₃/SiN_x layers, results demonstrated that the surface reflection property can be effectively optimized by adding a SiN_x layer, leading to the improvement in the final photovoltaic characteristic of the N-type solar cells.

Isotope source energy deposition along the thickness direction of a semiconductor is calculated, based upon which an ideal short current is evaluated for betavoltaic batteries. Electron-hole pair recombination and drifting length in a PN junction built-in electric field are extracted by comparing the measured short currents with the ideal short currents. A built-in electric field thickness design principle is proposed for betavoltaic batteries: after measuring the energy deposition depth and the carrier drift length, the shorter one should then be chosen as the built-in electric field thickness. If the energy deposition depth is much larger than the carrier drift length, a multijunction is preferred in betavoltaic batteries and the number of the junctions should be the value of the deposition depth divided by the drift length.

A new approach based on microcantilevers is presented to detect infrared photons with high sensitivity. Infrared photons are measured by monitoring the amplitude change of a vibrating microcantilever under light pressure force. The irradiating light is modulated into sinusoidal and pulsed waves, and to be in-phase and anti-phase with the cantilever driving signal. A linear relationship between the amplitude change of the cantilever and the light power distributing on the cantilever was observed. Under a vacuum of 10^-4 Pa, an infrared light power of 7.4 nW was detected with the cantilever. The in-phase and anti-phase modulation to the cantilever vibration using a pulsed light results in an enhanced response of the cantilever.

Along with a series of research works on the physical prototype and properties of the memory cell, an SPICE model for phase-change memory (PCM) simulations based on Verilog-A language is presented. By handling it with the heat distribution algorithm, threshold switching theory and the crystallization kinetic model, the proposed SPICE model can effectively reproduce the physical behaviors of the phase-change memory cell. In particular, it can emulate the cell's temperature curve and crystallinity profile during the programming process, which can enable us to clearly understand the PCM's working principle and program process.

This paper describes using a high-speed continuous-time analog adaptive equalizer as the front-end of a receiver for a high-speed serial interface, which is compliant with many serial communication specifications such as USB2.0, PCI-E2.0 and Rapid IO. The low and high frequency loops are merged to decrease the effect of delay between the two paths, in addition, the infinite input impedance facilitates the cascade stages in order to improve the high frequency boosting gain. The implemented circuit architecture could facilitate the wide frequency range from 1 to 3.3 Gbps with different length FR4-PCB traces, which brings as much as 25 dB loss. The replica control circuits are injected to provide a convenient way to regulate common-mode voltage for full differential operation. In addition, AC coupling is adopted to suppress the common input from the forward stage. A prototype chip was fabricated in 0.18-μm 1P6M mixed-signal CMOS technology. The actual area is 0.6 × 0.57 mm² and the analog equalizer operates up to 3.3 Gbps over FR4-PCB trace with 25 dB loss. The overall power dissipation is approximately 23.4 mW.

This paper presents an 8th order active-RC elliptic low-pass filter (LPF) for a direct conversion China Mobile Multimedia Broadcasting (CMMB) tuner with a 1 or 4 MHz -3 dB cutoff frequency (f_-3dB). By using a novel gain-bandwidth-product (GBW) extension technique in designing the operational amplifiers (op-amps), the proposed filter achieves 71 dB stop-band rejection at 1.7f_-3dB to meet the stringent CMMB adjacent channel rejection (ACR) specifications while dissipates only 2.8 mA/channel from a 3 V supply, its bias current can be further lowered to 2 mA/channel with only 0.5 dB peaking measured at the filter's pass-band edge. Elaborated common-mode (CM) control circuits are applied to the filter op-amp to increase its common-mode rejection ratio (CMRR) and effectively reject the large signal common-mode interference. Measurement results show that the filter has 128 dBμV_rms in-band IIP3 and more than 80 dB passband CMRR. Fabricated in a 0.35-μm SiGe BiCMOS process, the proposed filter occupies a 1.19 mm² die area.

A broadband frequency doubler using left-handed nonlinear transmission lines (LH NLTLs) based on MMIC technology is reported for the first time. The second harmonic generation on LH NLTLs was analyzed theoretically. A four-section LH NLTL which has a layout of 5.4 × 0.8 mm² was fabricated on GaAs semi-insulating substrate. With 20-dBm input power, the doubler obtained 6.33 dBm peak output power at 26.8 GHz with 24-43 GHz -6 dBm bandwidth. The experimental results were quite consistent with the simulated results. The compactness and the broad band characteristics of the circuit make it well suit for GaAs RF/MMIC application.

A 2.4 GHz low-power, low-noise and highly linear receiver front-end with a low noise amplifier (LNA) and balun optimization is presented. Direct conversion architecture is employed for this front-end. The on-chip balun is designed for single-to-differential conversion between the LNA and the down-conversion mixer, and is optimized for the best noise performance of the front-end. The circuit is implemented with 0.35 μm SiGe BiCMOS technology. The front-end has three gain steps for maximization of the input dynamic range. The overall maximum gain is about 36 dB. The double-sideband noise figure is 3.8 dB in high gain mode and the input referred third-order intercept point is 12.5 dBm in low gain mode. The down-conversion mixer has a tunable parallel R-C load at the output and an emitter follower is used as the output stage for testing purposes. The total front-end dissipation is 33 mW under a 2.85 V supply and occupies a 0.66 mm² die size.

This paper presents an improved merged architecture for a low-IF GNSS receiver frontend, where the bias current and functions are reused in a stacked quadrature LNA-mixer-VCO. Only a single spiral inductor is implemented for the LC resonator and an extra 1/2 frequency divider is added as the quadrature LO signal generator. The details of the design are presented. The gain plan and noise figure are discussed. The phase noise, quadrature accuracy and power consumption are improved. The test chip is fabricated though a 0.18 μm RF CMOS process. The measured noise figure is 5.4 dB on average, with a gain of 43 dB and a IIP3 of -39 dBm. The measured phase noise is better than -105 dBc/Hz at 1 MHz offset. The total power consumption is 19.8 mW with a 1.8 V supply. The experimental results satisfy the requirements for GNSS applications.

A fully integrated high linearity differential power amplifier driver with an on-chip transformer in a standard 0.13-μ m CMOS process for W-CDMA application is presented. The transformer not only accomplishes output impedance matching, but also acts as a balun for converting differential signals to single-ended ones. Under a supply voltage of 3.3 V, the measured maximum power is larger than 17 dBm with a peak power efficiency of 21%. The output power at the 1-dB compression point and the power gain are 12.7 dBm and 13.2 dB, respectively. The die size is 0.91 × 1.12 mm².

A low voltage, highly linear transconductance-C(G_m-C) low-pass filter for wireless local area network (WLAN) transceiver application is proposed. This transmitter (Tx) filter adopts a 9.8 MHz 3rd-order Chebyshev low pass prototype and achieves 35 dB stop-band attenuation at 30 MHz frequency. By utilizing pseudo-differential linear-region MOS transconductors, the filter IIP₃ is measured to be as high as 9.5 dBm. Fabricated in a 0.35 μ m standard CMOS technology, the proposed filter chip occupies a 0.41 × 0.17 mm² die area and consumes 3.36 mA from a 3.3-V power supply.

This paper presents three new types of pulse quenching mechanism (NMOS-to-PMOS, PMOS-to-NMOS and NMOS-to-NMOS) and verifies them using 3-D TCAD mixed mode simulations at the 90 nm node. The three major contributions of this paper are: (1) with the exception of PMOS-to-PMOS, pulse quenching is also prominent for PMOS-to-NMOS and NMOS-to-NMOS in a 90 nm process. (2) Pulse quenching in general correlates weakly with ion LET, but strongly with incident angle and layout style (i.e. spacing between transistors and n-well contact area). (3) Compact layout and cascaded inverting stages can be utilized to promote SET pulse quenching in combinatorial circuits.

Traditional feedforward structures suffer from performance constraints caused by the complex adder before quantizer. This paper presents an improved 4th-order 1-bit sigma-delta modulator which has a simple adder and delayed input feedforward to relax timing constraints and implement low-distortion. The modulator was fabricated in a 0.35 μ m CMOS process, and it achieve 92.8 dB SNDR and 101 dB DR with a signal bandwidth of 100 kHz dissipating 8.6 mW power from a 3.3-V supply. The performance satisfies the requirements of a GSM system.

A 2-Gsample/s 8-b analog-to-digital converter in 0.35 μm BiCMOS process technology is presented. The ADC uses the unique folding and interpolating algorithm and dual-channel timing interleave multiplexing technology to achieve a sampling rate of 2 GSPS. Digital calibration technology is used for the offset and gain corrections of the S/H circuit, the offset correction of preamplifier, and the gain and clock phase corrections between channels. As a result of testing, the ADC achieves 7.32 ENOB at an analog input of 484 MHz and 7.1 ENOB at Nyquist input after the chip is self-corrected.

We propose a hierarchical interconnection network with two-phase bufferless resonant clock distribution, which mixes the advantages of mesh and tree architectures. The problems of skew reduction and variation-tolerance in the mixed interconnection network are studied through a pipelined multiplier under a TSMC 65 nm standard CMOS process. The post-simulation results show that the hierarchical architecture reduces more than 75% and 65% of clock skew compared with pure mesh and pure H-tree networks, respectively. The maximum skew in the proposed clock distribution is less than 7 ps under imbalanced loading and PVT variations, which is no more than 1% of the clock cycle of about 760 ps.

Amorphous/crystalline silicon heterojunctions (a-Si:H/c-Si SHJ) were prepared by plasma-enhanced chemical vapor deposition (PECVD). The influence of the initial transient state of the plasma and the hydrogen pre-treatment on the interfacial properties of the heterojunctions was studied. Experimental results indicate that: (1) The instability of plasma in the initial stage will damage the surface of c-Si. Using a shutter to shield the substrate for 100 s from the starting discharge can prevent the influence of the instable plasma process on the Si surface and also the interface between a-Si and c-Si. (2) The effect of hydrogen pre-treatment on interfacial passivation is constrained by the extent of hydrogen plasma bombardment and the optimal time for hydrogen pre-treatment is about 60 s.