An ultra high-speed 8-bit timing interleave folding & interpolating analog-to-digital converter with digital foreground calibration technology

Zhang Zhengping; Wang Yonglu; Huang Xingfa; Shen Xiaofeng; Zhu Can; Zhang Lei; Yu Jinshan; Zhang Ruitao

doi:10.1088/1674-4926/32/9/095010

J. Semicond. > 2011, Volume 32 > Issue 9 > 095010

SEMICONDUCTOR INTEGRATED CIRCUITS

An ultra high-speed 8-bit timing interleave folding & interpolating analog-to-digital converter with digital foreground calibration technology

Zhang Zhengping, Wang Yonglu, Huang Xingfa, Shen Xiaofeng, Zhu Can, Zhang Lei, Yu Jinshan and Zhang Ruitao

+ Author Affiliations

DOI: 10.1088/1674-4926/32/9/095010

Abstract: A 2-Gsample/s 8-b analog-to-digital converter in 0.35 μm BiCMOS process technology is presented. The ADC uses the unique folding and interpolating algorithm and dual-channel timing interleave multiplexing technology to achieve a sampling rate of 2 GSPS. Digital calibration technology is used for the offset and gain corrections of the S/H circuit, the offset correction of preamplifier, and the gain and clock phase corrections between channels. As a result of testing, the ADC achieves 7.32 ENOB at an analog input of 484 MHz and 7.1 ENOB at Nyquist input after the chip is self-corrected.

Key words: ultra high-speed, interpolation algorithm, folding, analog-to-digital converter

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Zhang Zhengping, Wang Yonglu, Huang Xingfa, Shen Xiaofeng, Zhu Can, Zhang Lei, Yu Jinshan, Zhang Ruitao. An ultra high-speed 8-bit timing interleave folding & interpolating analog-to-digital converter with digital foreground calibration technology[J]. Journal of Semiconductors, 2011, 32(9): 095010. doi: 10.1088/1674-4926/32/9/095010

Zhang Z P, Wang Y L, Huang X F, Shen X F, Zhu C, Zhang L, Yu J S, Zhang R T. An ultra high-speed 8-bit timing interleave folding & interpolating analog-to-digital converter with digital foreground calibration technology[J]. J. Semicond., 2011, 32(9): 095010. doi: 10.1088/1674-4926/32/9/095010.

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Received: 20 August 2015 Revised: 19 April 2011 Online: Published: 01 September 2011

A 2-Gsample/s 8-b analog-to-digital converter in 0.35 μm BiCMOS process technology is presented. The ADC uses the unique folding and interpolating algorithm and dual-channel timing interleave multiplexing technology to achieve a sampling rate of 2 GSPS. Digital calibration technology is used for the offset and gain corrections of the S/H circuit, the offset correction of preamplifier, and the gain and clock phase corrections between channels. As a result of testing, the ADC achieves 7.32 ENOB at an analog input of 484 MHz and 7.1 ENOB at Nyquist input after the chip is self-corrected.

An ultra high-speed 8-bit timing interleave folding & interpolating analog-to-digital converter with digital foreground calibration technology

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