| Citation: |
Lin Lijuan, Jiang Lingli, Fan Hang, Zhang Bo. Impact of parasitic resistance on the ESD robustness of high-voltage devices[J]. Journal of Semiconductors, 2012, 33(1): 014005. doi: 10.1088/1674-4926/33/1/014005
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Lin L J, Jiang L L, Fan H, Zhang B. Impact of parasitic resistance on the ESD robustness of high-voltage devices[J]. J. Semicond., 2012, 33(1): 014005. doi: 10.1088/1674-4926/33/1/014005.
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Impact of parasitic resistance on the ESD robustness of high-voltage devices
DOI: 10.1088/1674-4926/33/1/014005
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Abstract
The impacts of substrate parasitic resistance and drain ballast resistance on electrostatic discharge (ESD) robustness of LDMOS are analyzed. By increasing the two parasitic resistances, the ESD robustness of LDMOS are significantly improved. The proposed structures have been successfully verified in a 0.35 μm BCD process without using additional process steps. Experimental results show that the second breakdown current of the optimal structure increases to 3.5 A, which is about 367% of the original device. -
References
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