J. Semicond. > 2013, Volume 34 > Issue 1 > 014002
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SEMICONDUCTOR DEVICES

Analysis of the subthreshold characteristics of vertical tunneling field effect transistors

Zhongfang Han, Guoping Ru and Gang Ruan

+ Author Affiliations

 Corresponding author: Ru Guoping, Email:gpru@fudan.edu.cn

DOI: 10.1088/1674-4926/34/1/014002

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Abstract: Subthreshold characteristics of vertical tunneling field effect transistors (VTFETs) with an n+-pocket in the p+-source are studied by simulating the transfer characteristics with a commercial device simulator. Three types of subthreshold characteristics are demonstrated for the device with different pocket thicknesses and doping concentrations. Band diagram analysis shows that such a VTFET can be treated as a gate-controlled tunnel diode connected in series with a conventional n-channel metal-oxide-semiconductor FET. This VTFET can work either as a TFET or an n-MOSFET in the subthreshold region, depending on the turn-on sequence of these two components. To our knowledge, this is the first time such a device model has been used to explain the subthreshold characteristics of this kind of VTFET and the simulation results demonstrate that such a device model is convictive and valid. Our results indicate that the design of the n+ pocket is crucial for such a VTFET in order to achieve ultra-steep turn-on characteristics.

Key words: tunneling field effect transistor, metal-oxide-semiconductor field effect transistor, subthreshold swing



[1]
Seabaugh A C. Low-voltage tunnel transistors for beyond CMOS logic. Proc IEEE, 2010, 98(12):2095 doi: 10.1109/JPROC.2010.2070470
[2]
Woo R. Band-to-band tunneling transistor scaling and design for low-power logic applications. PhD Dissertation, Stanford University, 2009
[3]
Reddick W M, Amaratunga G A J. Silicon surface tunnel transistor. Appl Phys Lett, 1995, 67(4):494 doi: 10.1063/1.114547
[4]
Toriumi A, Koga J. Negative differential conductance in three-terminal silicon tunneling device. Appl Phys Lett, 1996, 69(10):1435 doi: 10.1063/1.117606
[5]
Wang P F, Nirschl T, Schmitt-Landsiedel D, et al. Simulation of the Esaki-tunneling FET. Solid-State Electron, 2003, 47(7):1187 doi: 10.1016/S0038-1101(03)00045-5
[6]
Han Z F, Ru G P, Ruan G. A simulation study of vertical tunnel field effect transistors. Proceedings of IEEE 9th International Conference on ASIC (ASICON), 2011: 665
[7]
Park B G, Choi W Y, Lee J D, et al. Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec. IEEE Electron Device Lett, 2007, 28(8):743 doi: 10.1109/LED.2007.901273
[8]
Bowonder A, Patel P, Jeon K, et al. Low voltage green transistor using ultra shallow junction and hetero tunneling. Extended Abstracts of IEEE 8th International Workshop on Junction Technology, 2008: 93
[9]
Bowonder A, Patel P, Jeon K, et al. Low-voltage green transistor using hetero-tunneling. Proceedings of IEEE Silicon Nanoelectronics Workshop, 2008: 5
[10]
Hu C, Chou D, Patel P, et al. Green transistor——a VDD scaling path for future low power ICs. Proceedings of IEEE International Symposium on VLSI Technology, Systems and Applications, 2008: 14
[11]
Patel P, Jeon K, Bowonder A, et al. A low voltage steep turn-off tunnel transistor design. Proceedings of IEEE 2009 International Conference on Simulation of Semiconductor Processes and Devices, 2009: 23
[12]
Kao K H, Verhulst A S, Vandenberghe W G. Direct and indirect band-to-band tunneling. IEEE Trans Electron Devices, 2012, 59(2):292 doi: 10.1109/TED.2011.2175228
[13]
Nayfeh O M, Chleirigh C N, Hennessy J, et al. Design of tunneling field-effect transistors using strained-silicon/strained-germanium type-Ⅱ staggered heterojunctions. IEEE Electron Device Lett, 2008, 29(9):1074 doi: 10.1109/LED.2008.2000970
[14]
Hu C. Green transistor as a solution to the IC power crisis. Proceedings of IEEE 9th International Conference on Solid-State and Integrated-Circuit Technology, 2008:17
[15]
Hu C. Reduce IC power consumption by > 10x with a green transistor. Proceedings of Device Research Conference, 2009:9
[16]
http://www.crosslight.com for information about APSYS
Fig. 1.  (a) Conventional LTFET structure, a gate-controlled p–i–n diode where tunneling occurs along the gate–semiconductor interface. (b) VTFET structure[1], where the tunneling is perpendicular to the gate interface. (c) VTFET structure[13], in which an n$^{+}$ pocket is located within the p$^{+}$ source and connected to the n$^{+}$ drain through an inversion channel.

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Fig. 2.  (a) OFF-state and ON-state band diagrams of LTFET, when in the "OFF" state, the tunneling barrier is too thick for electrons to tunnel through, when in the "ON" state, the tunneling barrier is thinned enough by the gate voltage for the electrons to tunnel through. (b) OFF-state and ON-state band diagrams of VTFET, the tunneling barrier can already be thin enough ( < 10 nm) when it is in the "OFF" state, but there is no overlap between the conduction band and valence band of the tunnel junction, The tunneling barrier is lowered by the gate voltage when it is in the "ON" state for electrons to tunnel through.

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Fig. 3.  Schematic of the VTFET structure simulated in this paper. The source, substrate, and drain are p-type doped with 1 $\times$ 10$^{20}$ cm$^{-3}$, p-type doped with 1 $\times$ 10$^{17}$ cm$^{-3}$, and n-type doped with 1 $\times$ 10$^{20}$ cm$^{-3}$, respectively.

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Fig. 4.  Simulated $I_{\rm d}$–$V_{\rm g}$ characteristics of VTFETs with various pocket thicknesses.

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Fig. 5.  Device model of a VTFET, the VTFET can be treated as a conventional MOSFET in series with a tunnel diode.

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Fig. 6.  (a) Band diagrams at $V_{\rm g}$ $=$ 0 V along cutline A in Fig. 1(c). (b) Band diagrams at $V_{\rm g}$ $=$ 1 V along cutline A in Fig. 1(c). (c) Band diagrams at $V_{\rm g}$ $=$ 1 V along cutline B in Fig. 1(c). (d) Two-dimensional conduction band at $V_{\rm g}$ $=$ 1 V. (e) Three-dimensional conduction band at $V_{\rm g}$ $=$ 1 V.

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Fig. 7.  (a) Band diagrams at $V_{\rm g}$ $=$ –1 V along cutline A in Fig. 1(c). (b) Band diagrams at $V_{\rm g}$ $=$ $-0.5$ V along cutline A in Fig. 1(c). (c) Band diagrams at $V_{\rm g}$ $=$ $-0.5$ V along cutline B in Fig. 1(c). (d) Two-dimensional conduction band at $V_{\rm g}$ $=$ $-0.5$ V. (e) Three-dimensional conduction band at $V_{\rm g}$ $=$ $-0.5$ V.

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Fig. 8.  (a) Band diagrams at $V_{\rm g}$ $=$ –1.2 V along cutline A in Fig. 1(c). (b) Band diagrams at $V_{\rm g}$ $=$ $-1.2$ V along cutline B in Fig. 1(c). (c) Two-dimensional conduction band at $V_{\rm g}$ $=$ $-1.2$ V. (d) Three-dimensional conduction band at $V_{\rm g}$ $=$ $-1.2$ V.

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Fig. 9.  Simulated $I_{\rm d}$–$V_{\rm g}$ characteristics of VTFET with various pocket doping concentrations.

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Table 1.   Subthreshold swing of VTFETs with a fixed pocket doping concentration of 5 $\times$ 10$^{19}$ cm$^{-3}$.

Table 2.   Subthreshold swing of VTFETs with a fixed pocket thickness of 5 nm.
[1]
Seabaugh A C. Low-voltage tunnel transistors for beyond CMOS logic. Proc IEEE, 2010, 98(12):2095 doi: 10.1109/JPROC.2010.2070470
[2]
Woo R. Band-to-band tunneling transistor scaling and design for low-power logic applications. PhD Dissertation, Stanford University, 2009
[3]
Reddick W M, Amaratunga G A J. Silicon surface tunnel transistor. Appl Phys Lett, 1995, 67(4):494 doi: 10.1063/1.114547
[4]
Toriumi A, Koga J. Negative differential conductance in three-terminal silicon tunneling device. Appl Phys Lett, 1996, 69(10):1435 doi: 10.1063/1.117606
[5]
Wang P F, Nirschl T, Schmitt-Landsiedel D, et al. Simulation of the Esaki-tunneling FET. Solid-State Electron, 2003, 47(7):1187 doi: 10.1016/S0038-1101(03)00045-5
[6]
Han Z F, Ru G P, Ruan G. A simulation study of vertical tunnel field effect transistors. Proceedings of IEEE 9th International Conference on ASIC (ASICON), 2011: 665
[7]
Park B G, Choi W Y, Lee J D, et al. Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec. IEEE Electron Device Lett, 2007, 28(8):743 doi: 10.1109/LED.2007.901273
[8]
Bowonder A, Patel P, Jeon K, et al. Low voltage green transistor using ultra shallow junction and hetero tunneling. Extended Abstracts of IEEE 8th International Workshop on Junction Technology, 2008: 93
[9]
Bowonder A, Patel P, Jeon K, et al. Low-voltage green transistor using hetero-tunneling. Proceedings of IEEE Silicon Nanoelectronics Workshop, 2008: 5
[10]
Hu C, Chou D, Patel P, et al. Green transistor——a VDD scaling path for future low power ICs. Proceedings of IEEE International Symposium on VLSI Technology, Systems and Applications, 2008: 14
[11]
Patel P, Jeon K, Bowonder A, et al. A low voltage steep turn-off tunnel transistor design. Proceedings of IEEE 2009 International Conference on Simulation of Semiconductor Processes and Devices, 2009: 23
[12]
Kao K H, Verhulst A S, Vandenberghe W G. Direct and indirect band-to-band tunneling. IEEE Trans Electron Devices, 2012, 59(2):292 doi: 10.1109/TED.2011.2175228
[13]
Nayfeh O M, Chleirigh C N, Hennessy J, et al. Design of tunneling field-effect transistors using strained-silicon/strained-germanium type-Ⅱ staggered heterojunctions. IEEE Electron Device Lett, 2008, 29(9):1074 doi: 10.1109/LED.2008.2000970
[14]
Hu C. Green transistor as a solution to the IC power crisis. Proceedings of IEEE 9th International Conference on Solid-State and Integrated-Circuit Technology, 2008:17
[15]
Hu C. Reduce IC power consumption by > 10x with a green transistor. Proceedings of Device Research Conference, 2009:9
[16]
http://www.crosslight.com for information about APSYS

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    Received: 01 April 2012 Revised: 02 August 2012 Online: Published: 01 January 2013

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      Article Navigation >  Journal of Semiconductors  > 2013  >  34(1): 014002
      Zhongfang Han, Guoping Ru, Gang Ruan. Analysis of the subthreshold characteristics of vertical tunneling field effect transistors[J]. Journal of Semiconductors, 2013, 34(1): 014002. doi: 10.1088/1674-4926/34/1/014002 ****Z F Han, G P Ru, G Ruan. Analysis of the subthreshold characteristics of vertical tunneling field effect transistors[J]. J. Semicond., 2013, 34(1): 014002. doi: 10.1088/1674-4926/34/1/014002.
      Citation:
      Zhongfang Han, Guoping Ru, Gang Ruan. Analysis of the subthreshold characteristics of vertical tunneling field effect transistors[J]. Journal of Semiconductors, 2013, 34(1): 014002. doi: 10.1088/1674-4926/34/1/014002 ****
      Z F Han, G P Ru, G Ruan. Analysis of the subthreshold characteristics of vertical tunneling field effect transistors[J]. J. Semicond., 2013, 34(1): 014002. doi: 10.1088/1674-4926/34/1/014002.
      shu

      Analysis of the subthreshold characteristics of vertical tunneling field effect transistors

      DOI: 10.1088/1674-4926/34/1/014002

      • State Key Laboratory of ASIC and System, Department of Microelectronics, Fudan University, Shanghai 200433, China

      Funds:

      Project supported by the International Research Training Group

      the International Research Training Group 

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      • Corresponding author: Ru Guoping, Email:gpru@fudan.edu.cn
      • Received Date: 2012-04-01
      • Revised Date: 2012-08-02
      • Published Date: 2013-01-01

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