1. Introduction

With the rapid development of semiconductor integrated circuit technology, the venture induced by an ESD (electrostatic discharge) in ICs is becoming increasingly severe. Due to the extensive use of HV (high voltage) devices in smart power technologies, such as the display driver IC, power supply, power management and automotive electronics, ESD performance has become an important issue in the design of HV devices. To sustain the required ESD levels, ESD protection devices are often designed with large device dimensions, which are often drawn with a multi-finger layout style to reduce the total occupied silicon area^[1]. Typically, multi-finger GG-nLDMOS (gate-grounded n-channel lateral double-diffused metal–oxide–semiconductor) devices are widely used as ESD protection devices in the HV process owing to the effectiveness of the parasitic n–p–n BJT (bipolar junction transistor) of the GG-nLDMOS in handling high ESD currents. Figure 1 shows the circuit diagram of the multi-finger GG-nLDMOS. The finger number can be changed to achieve different ESD levels. However, previous studies^[2-5] have mentioned that under ESD stress, a few fingers may be triggered on first, and these first turned-on fingers are more vulnerable to thermal breakdown, resulting in non-uniform conduction of all the fingers.

Several approaches have been proposed to successfully suppress the non-uniform turn-on phenomenon, such as the substrate-triggered technique^[6] and gate-coupled technique^[3]. However, these techniques need additional trigger circuits, which increase the design venture and difficulty. In this paper, an effective approach without an additional trigger circuit has been proposed through increasing the substrate resistance to improve the turn-on uniformity of the HV multi-finger GG-nLDMOS and is successfully verified in a 0.35 $\mu$m 40 V BCD (bipolar-CMOS-DMOS) process.

2. A conventional 40 V GG-nLDMOS

A cross section of the conventional 40 V GG-nLDMOS device is shown in Fig. 2(a). As shown in the figure, the drain is defined as N+/LVNW/HVNW; the channel is defined as the PW, which is under the poly gate; the source is defined as the N$^+$ implanted region in the PW; the substrate contact is defined as the P$^+$ implanted region in the PW. Figure 2(b) shows the layout top-view of a conventional four-finger GG-nLDMOS. As shown in the figure, due to the case that each finger has a corresponding PW, each finger needs a corresponding substrate contact, which is formed by the P$^+$ implanted region in the corresponding PW of each finger. The substrate contacts of the middle two fingers are overlapped to decrease the layout area. This layout style can make the base resistance of each parasitic lateral n–p–n BJT in the multi-finger GG-nLDMOS approximately equal and suppress the non-uniform turn-on phenomenon caused by the difference in the base resistance of each parasitic BJT in the multi-finger GG-nLDMOS.

Considering the case when a positive ESD pulse is applied to the drain terminal of the GG-nLDMOS with the source, gate and substrate shortened to ground, the schematic of the $I$–$V$ (current–voltage) characteristic is shown in Fig. 3. The device is off until the drain breakdown voltage is reached. Then, an avalanche breakdown occurs at the reverse biased PN junction (HVNW/PW) and generates a large amount of electron-hole pairs. The electrons are collected by the drain terminal and the holes flow into the ground via the substrate contact. The avalanche current $I_{\rm gen}$ flows through the parasitic $R_{\rm B}$ and raises the potential of the PW, thus a potential drop is formed between the PW and the source terminal. To turn on the parasitic NPN transistor, the avalanche current $I_{\rm gen}$ is required to meet the formula:

$$\begin{equation} \label{eq1} I_{\rm gen} =I_{\rm B} \cong \frac{V_{\rm on} }{R_{\rm B}}, \end{equation}$$

(1)

in which, $V_{\rm on}$ is the forward turn-on voltage of the PW and source N$^+$ junction (about 0.7 V).

After the parasitic NPN transistor is triggered, continuous stressing will drive the parasitic NPN transistor into the deep snapback region and a low resistance current discharge channel will be formed. Then the drain current continues increasing and heat accumulates in the device, which eventually leads to the second breakdown of the device. The corresponding second breakdown voltage and current are recorded as $V_{\rm t2}$ and $I_{\rm t2}$, as shown in Fig. 3.

The TLP (transmission line pulsing) test results of a two-finger, four-finger and six-finger conventional 40 V GG-nLDMOS are shown in Fig. 4 (the second breakdown current $I_{\rm t2}$ is the drain current that corresponds to the leakage current, which is closest to but not more than 10$^{-7}$A). Each finger has the same channel width of 75 $\mu$m and channel length of 2.5 $\mu$m. As shown in the figure, the turn on voltage $V_{\rm t1s}$ of the two-finger, four-finger and six-finger conventional GG-nLDMOS devices are the same, 60 V; the second breakdown current $I_{\rm t2s}$ are 0.86 A, 1.14 A and 1.2 A, respectively. Compared with the two-finger conventional GG-nLDMOS, the $I_{\rm t2s}$ of the four-finger and six-finger conventional devices increase by 33% and 40% respectively, which are much lower than the increasing proportions of $I_{\rm t2s}$ of completely uniform turn-on four-finger and six-finger devices (compared with the two-finger completely uniform turn-on device, the increasing $I_{\rm t2s}$ proportions of the four-finger and six-finger devices are 100% and 200%, respectively). These indicate that this 40 V conventional multi-finger GG-nLDMOS device suffers a serious non-uniform turn-on problem.

3. Optimization

For the conventional 40 V multi-finger GG-nLDMOS devices in this paper, the trigger voltage $V_{\rm t1}$ is greater than the second breakdown voltage $V_{\rm t2}$. It is easy to imagine that the first turned-on fingers start to discharge the ESD pulse and then reach its damage threshold before the remaining fingers come into play. Actually, when the ESD stress is applied to the multi-finger GG-nLDMOS, the ESD current flowing through the first turned-on fingers may provide a trigger current for the neighboring fingers, making them probably turn on with the drain voltage lower than the trigger voltage $V_{\rm t1}$^[7]. From Eq. (1), it can be concluded that the larger the substrate resistance $R_{\rm B}$ is, the smaller the trigger current $I_{\rm gen}$ is needed. So by means of increasing the substrate resistance $R_{\rm B}$, this paper has proposed an optimized 40 V GG-nLDMOS device structure to improve the turn-on uniformity of the 40 V multi-finger GG-nLDMOS, which is shown in Fig. 5.

Compared with the conventional 40 V GG-nLDMOS, the optimized 40 V GG-nLDMOS extends the space between the substrate contact P$^+$ region and the source N$^+$ region. Meanwhile, the area of the substrate contact P$^+$ region is reduced to 1/3 of the conventional one, as shown in Fig. 6. The remaining parameters are unchanged. In this optimized GG-nLDMOS structure, extending the space between the source and the substrate contact increases the distance from the channel region to the substrate contact. So, the flowing path of the avalanche current becomes longer and the substrate resistance $R_{\rm B}$ becomes larger. The reduction in area of the substrate contact increases the flowing path length of the avalanche current that flows through area A (shown in Fig. 6). So, the substrate resistance of the paths between the substrate contacts and the base of the parasitic transistor at region A becomes larger. Fujiwara^[8] has proven that compared with the conventional one-finger HV GG-nLDMOS, the turn-on uniformity and ESD robustness of the optimized one-finger HV GG-nLDMOS, which has an extended source diffusion width and an island shape body contact (a similar approach to this paper to increase substrate resistance), are improved.

Figure 7 shows the TLP test results of the two-finger, four-finger and six-finger optimized 40 V GG-nLDMOS. As shown in the figure, the $V_{\rm t1s}$ of these three optimized GG-nLDMOS devices are the same, 49 V; the $I_{\rm t2s}$ are 1.06 A, 1.69 A and 2.53 A, respectively. Compared with the two-finger optimized GG-nLDMOS, the $I_{\rm t2s}$ of the four-finger and six-finger optimized devices increase by 60% and 139% respectively, which are much larger than the increasing proportions of $I_{\rm t2s}$ of the four-finger and six-finger conventional GG-nLDMOS.

The summary TLP test results of conventional and optimized 40 V GG-nLDMOS are shown in Table 1. It is clearly shown that compared with the conventional GG-nLDMOS, the $V_{\rm t1}$ of the optimized device is reduced by 11 V; with the same two finger number, the $I_{\rm t2}$ of the optimized device increases by 23%; with the same four finger number, the $I_{\rm t2}$ of the optimized device increases by 48%; with the same six finger number, the $I_{\rm t2}$ of the optimized device increases by 110%. From the analyzes of the above data, it can be concluded that compared with the conventional 40 V GG-nLDMOS, the turn-on uniformity and ESD robustness are improved in the optimized multi-finger 40 V GG-nLDMOS. However, increasing the substrate resistance $R_{\rm B}$ has its side effects, such as increasing the layout area of the device.

The $I_{\rm t2s}$ of GG-nLDMOS devices with different $D$ (distance between source and substrate contact) are shown in Fig. 8. The four devices have the same width 75 $\mu$m $\times$ 4 finger. They also have the same substrate contact structure, the area of which is decreased to 1/3 of the conventional GG-nLDMOS. As shown in the figure, the $I_{\rm t2}$ of the GG-nLDMOS increases as $D$ increases. The increase of $D$ leads to an increase in the substrate resistance $R_{\rm B}$. So it can be concluded that within a certain range, the larger the substrate resistance $R_{\rm B}$ is, the more uniformly the GG-nLDMOS will be turned on.

4. Conclusion

Due to the non-uniform turn-on characteristics, high-voltage multi-finger GG-nLDMOS devices can't reach the required ESD level by simply increasing the device area. This paper has optimized the device layout by increasing the substrate resistance $R_{\rm B}$ to effectively improve the turn-on uniformity of the multi-finger GG-nLDMOS, which has been successfully verified in a 0.35 $\mu$m 40 V BCD process. This approach doesn't need another trigger circuit, which reduces the design venture and difficulty. The TLP test results reveal that a conventional 40 V multi-finger GG-nLDMOS suffers a serious non-uniform turn-on problem and the turn-on uniformity and ESD robustness are improved in the optimized 40 V multi-finger GG-nLDMOS. The influence of a different $R_{\rm B}$ is also studied and it is found that within a certain range, the larger the substrate resistance $R_{\rm B}$ is, the more uniformly the GG-nLDMOS will be turned on.