Fig. 1.
Cross section of (a) a conventional LDMOS, (b) an SCR-LDMOS, (c) an equivalent circuit conventional LDMOS, and (d) an SCR-LDMOS.
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| Citation: |
Hongwei Pan, Siyang Liu, Weifeng Sun. A novel latch-up free SCR-LDMOS with high holding voltage for a power-rail ESD clamp[J]. Journal of Semiconductors, 2013, 34(1): 014007. doi: 10.1088/1674-4926/34/1/014007
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H W Pan, S Y Liu, W F Sun. A novel latch-up free SCR-LDMOS with high holding voltage for a power-rail ESD clamp[J]. J. Semicond., 2013, 34(1): 014007. doi: 10.1088/1674-4926/34/1/014007.
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A novel latch-up free SCR-LDMOS with high holding voltage for a power-rail ESD clamp
DOI: 10.1088/1674-4926/34/1/014007
More Information
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Abstract
The low snapback holding voltage of the SCR-LDMOS device makes it susceptible to latch-up failure, when used in power-rail ESD (electro-static discharge) clamp circuits. In order to eliminate latch-up risk, this work presents a novel SCR-LDMOS structure with an N-type implantation layer to achieve a 17 V holding voltage and a 5.2 A second breakdown current. The device has been validated using TLP measurement analysis and is applied to a power-rail ESD clamp in half-bridge driver ICs.-
Keywords:
- ESD protection,
- ESD robustness,
- SCR-LDMOS,
- latch-up,
- holding voltage
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References
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