1. Introduction

Wireless technologies have been developed for decades, and many standards were published in various fields to fulfill people's needs of communications. Chips accommodating these standards have exhibited drastic growth. GSM and WCDMA for mobile phones, 802.11 series for local data transfer and Bluetooth for personal device connections are good examples. Due to the advantages in functions and performances, these types of chips call for fine line process like 90 nm^[1], even 65 nm^[2], and high-end technology like SiGe or GaAs which leads to higher cost. While these types of radios still prosper, another type of radio, which is more customized has started to emerge on the market^[3-5]. The application areas usually include: remote keyless entry (RKE), automatic meter reading (AMR), building/home automation, low/medium quality voice communication, sensor network and supply chain surveillance. Chips used in these applications often rely on battery operation and are produced in large quantity, so they are very sensitive to both power consumption and cost. Chips of this type are commonly called short range device (SRD) because of their relatively short communication range compared to mainstream high-performance wireless radios.

The comprehensive application fields with no unified standards almost make the license-free industrial, scientific, and medical (ISM) band the compulsory choice for SRD. The popular ISM band includes 13.56 MHz, 433 MHz, 915 MHz, 2.4 GHz and 5.8 GHz. The 13.56 MHz is usually used for passive RFID with mutual inductance. 2.4 GHz band is already congested with many existing devices. Meanwhile, the 5.8 GHz band shows its weakness in permeability through obstacles. The remaining 433 MHz and 915 MHz bands seem to be more suitable for SRD. Firstly, the operation frequencies are ten times below cut-off frequencies of modern semiconductor technologies which relieves power constraints. Secondly, the longer wavelength exhibits less line of sight (LOS) effects. Several standards in these bands have been released. In Europe, ETSI EN 300 200 planned about 2 MHz bandwidth around 433 MHz and 868 MHz. In the United States, 902-928 MHz band is assigned by FCC as ISM band, which allows SRD devices. In Japan, ARIB STD-T67 also indicates 426, 449 and 469 MHz as ISM bands.

SRD devices are usually battery powered and disposable; a long battery life about 6-10 years is desired. Since SRD applications do not deal with a large amount of data, the T/R ratio is very low, which makes intrinsic power consumption of the chip crucial to battery life. So, low power design is extremely necessary to extend battery life. Besides that, mass production and disposable features make SRD chips impossible to use a high-end process like SiGe or GaAs. Mature and cheap CMOS technology is preferred. Meanwhile other bulky and expensive components like the SAW filter or external power management chip should be avoided too.

The receiver RF front-end proposed in this paper includes a differential LNA, a double-balanced mixer and a transimpedance amplifier. The chip was fabricated in CMOS 0.18 $\mu$m 1P5M process. This paper presents a short review of wideband LNA and discusses the proposed current-reuse LNA, and describes the other circuit designs of RF front-end.

2. Current-reuse wideband LNA design

2.1 Wideband LNA review

There are several architectures of wideband LNA. The most popular ones are resistive-negative-feedback and cross-coupled common-gate (CCC). The core part of these two types of LNA is shown in Fig. 1. The input impedance of the circuit in Fig. 1(a) is lowered by a negative feedback through $R_{\rm F}$, and in Fig. 1(b), the differential input impedance of the common-gate amplifier is simply 1/$g_{\rm m}$, and $g_{\rm m}$ is the transconductance of MN1 and MN2. With the additional cross-coupled capacitor, the small signal is cross-coupled to the gate of the transistor, so the small signal applied to the transistor is doubled compared to the normal common-gate amplifier. This will increase the equivalent $g_{\rm m}$ of the transistor. So the differential input impedance of the cross-coupled common-gate amplifier can be further lowered to $\frac{1}{2}$$g_{\rm m}$.

For fixed $R_{\rm F}$ and $R_{\rm S}$ in resistive-negative-feedback LNA, the gain is limited if input matching should be maintained, furthermore, the follower is not perfect, usually a source follower is used, which brings extra effects on input matching, noise and power dissipation. In CCC LNA, two ideal current sources are used to establish DC point and to prevent the RF input signal current from flowing into the ground. In a practical circuit, inductors are used to block the RF signal, but in the frequency band lower than 1 GHz, the inductor increases drastically and occupies large silicon areas, which is not cost effective. On the other hand, if the MOS current mirror is used to replace the inductor, an extra voltage margin is needed but makes no improvements in gain and noise performance. So, both architectures cannot meet the requirements of sub-1-GHz SRD applications.

2.2 Proposed circuit

The proposed current-reuse LNA in this paper uses an active feedback to boost the $g_{\rm m}$ of amplifying transistors. However, unlike the circuit in Ref. [6], bias current of active feedback is fully reused; no extra power is needed to make the feedback coefficient more than 1. The architecture of the LNA is shown in Fig. 2 (bias details are not shown).

The upper part of LNA is like common-gate (CG) LNA, MN1 and MN2 are $g_{\rm m}$ transistors; $R_{1}$ is resistive load providing wideband voltage gain. The lower part of LNA is totally different from conventional CGLNA. MP1, MP2 and $R_{2}$ serve as "auxiliary" amplifier, and a cross-coupled input is applied to MP2 and MP2. $V_{\rm CPL}$, the voltage generated by AC current flowing through $R_{2}$, is coupled to gates of MN1 and MN2. With a proper voltage gain of the auxiliary amplifier, the feedback coefficient to MN1 and MN2 can exceed 1, boosting the $g_{\rm m}$ of MN1 and MN2.

2.3 Voltage gain

To simplify the gain analysis, all MOSFETs are considered as $g_{\rm m}$ components. The gain of the main amplifier can be divided into two parts, the gain $G_{\rm s}$ caused by $V_{\rm I}$ at source of MN1 and MN2, the gain $G_{\rm g}$ caused by $V_{\rm CPL}$ at the gate of MN1 and MN2.

The $G_{\rm s}$ is exactly the voltage gain of CGLNA, and can be expressed as:

$$G_{\rm s} =g_{\rm mMN1, 2} R_1 .$$

(1)

$G_{\rm g}$ can be written as:

$$G_{\rm g} =A g_{\rm mMN1, \, 2} R_1 .$$

(2)

In Eq. (2), $A$ denotes the feedback coefficient, which is $V_{\rm CPL}$/$V_{\rm I}$. Due to the cross-coupling scheme, the effective transconductance of MP1 and MP2 are doubled, so A is shown in Eq. (3):

$$A=2 g_{\rm mMP1, 2} R_2.$$

(3)

Applying superposition method, the total gain of LNA is:

$$G_{\rm total} =g_{\rm mMN1, \, 2} \left( {1+2g_{\rm mMP1, \, 2} R_2} \right)R_1.$$

(4)

As we can see from Eq. (4), the total gain is boosted by "auxiliary" amplifier.

2.4 Input impedance

Incorporating with the current-reuse feedback part, the input impedance is quite different from CG LNA. The impedance consists of two separate parts. ZIN$_{\rm MP1, \, 2}$. The differential impedance looking into MP1 and MP2 is:

$${\rm ZIN}_{\rm MP1, \, 2} =\frac{1}{2g_{\rm mMP1, \, 2}}.$$

(5)

The impedance looking into MN1 and MN2, expressed as ZIN$_{\rm MN1, \, 2}$, is reduced by feedback from auxiliary amplifier, and can be written as:

$$\begin{equation} \label{eq6} {\rm ZIN}_{\rm MN1, \, 2} =\frac{1}{g_{\rm mMN1, \, 2} (1+2g_{\rm mMP1, \, 2} R_2 )}. \end{equation}$$

(6)

So the total impedance looking from input port can be expressed in the admittance format:

$$\begin{equation} \label{eq7} G_{\rm in} =2g_{\rm mMP1, \, 2} +g_{\rm mMN1, \, 2} (1+2g_{\rm mMP1, \, 2} R_2). \end{equation}$$

(7)

Compared to CG LNA, the input admittance is increased without extra DC penalty.

2.5 Noise analysis

The calculation of cross-coupled CG LNA is quite straightforward. There are two main noise sources, the transconductance transistors, contributing to the whole noise factor. However, in the proposed design, the situation is more complicated because the feedback branch is no longer a passive device, it contributes noise to total noise factor too. To simplify the analysis, the LNA is split from the input plane into lower part and upper part. The equivalent circuit is shown in Fig. 3.

Firstly, the output noise voltage from the lower part is checked. In Fig. 3, $\overline {I_{\rm np}^2}$ is the thermal channel noise, $\overline {V_{\rm n1}^2}$ is output noise voltage and can be expressed as:

$$\begin{equation} \label{eq8} \overline {V_{\rm n1}^2} =\overline {I_{\rm np}^2 }R_2^2 . \end{equation}$$

(8)

Because of feedback, the voltage noise is modeled as a voltage source applied to the gate of MN1 and MN2. The upper part of LNA is fully symmetrical, so a half circuit is used to analyze the noise. The half circuit is shown in Fig. 3(b). $\overline {V_{\rm n1}^2}$ represents the total noise of LNA.

$$\begin{equation} \label{eq9} V_{\rm n2}^2=4 \left( {\overline {I_{\rm nn}^2 } +\frac{1}{4}V_{\rm n1}^2 g_{\rm mMN1, \, 2}^2 } \right)R_1^2 . \end{equation}$$

(9)

Substituting Eq. (8) into Eq. (9), and dividing Eq. (9) by the voltage gain of upper part and 4$KTR_{\rm s}$, the noise factor can be derived as

$$\begin{equation} \begin{split} \label{eq10} F={}& 1+ \bigg[16KT\left( {\frac{\gamma }{\alpha }} \right)_{\rm n} g_{\rm m MN1, 2} +4KT\left( {\frac{\gamma }{\alpha }} \right)_{\rm p} \\[2mm]&{} \times g_{\rm m MP1, \, 2} g_{\rm mMN1, \, 2}^2 R_2^2 \bigg] \\[2mm]&{} \times\left[R_1^2 \left( {1+2g_{\rm m MP1, \, 2} R_2} \right)^24KTR_{\rm s}\right]^{-1}, \end{split} \end{equation}$$

(10)

where $\alpha$, $\gamma$ are well-known bias-and process-dependent parameters. If we assume $g_{\rm mMN1, \, 2}$ is twice $g_{\rm mMP1, \, 2}$, $g_{\rm mMP1, \, 2}$ $\gg$ 1, and ignore the noise generated by loading resistor, which is a minor noise contributor, Equation (10) can be further simplified to

$$\begin{equation} \label{eq11} F\approx 1+ \frac{4\left( {\dfrac{\gamma }{\alpha }} \right)_{\rm n} R_1^2 }{g_{\rm mMN1, \, 2} R_2^2 R_{\rm s}}+ \frac{\left( {\dfrac{\gamma }{\alpha }} \right)_{\rm p} g_{\rm mMN1, \, 2} R_1^2 }{2R_{\rm s}}. \end{equation}$$

(11)

From Eq. (11), the main noise source is no longer MN1 and MN2 but MP1 and MP2 because of $g_{\rm m}$ boosting.

3. Circuit implementation of the receiver

3.1 Receiver architecture

The implementation of the receiver is described in this section; the receiver is comprised of LNA, $g_{\rm m}$ converter, mixer, transimpedance amplifier (TIA) and output buffer. The receiver uses a low-IF architecture and IF frequency is chosen as 424 kHz to avoid flicker noise and to ease successive circuit design. The architecture of the receiver is shown in Fig. 4.

3.2 LNA

After the detailed analysis in the last section, the implementation of LNA is rather easy. Considering the tradeoff of current efficiency and output impedance, the $g_{\rm m}$ over $I_{\rm d}$ of MN1, MN2 and MP1, MP2 in Fig. 2 is chosen to be 12 V$^{-1}$. The four capacitors, $C_{1}$ and $C_{2}$, are 1.3 pF, which are much larger than parasitic capacitances at the gates of the transistors. This configuration makes voltage attenuation at the gates negligible. The $R_{2}$ takes a value of 450 $\Omega$, which pushes the pole at gates of MN1 and MN2 over 2 GHz. The $R_{1}$ is about 1.2 k$\Omega$, providing enough voltage gain and an acceptable pole at 1.5 GHz. The transconductance of MN1, MN2 and MP1, MP2 are set to 6 mS and 3 mS respectively. These parameters set the input impedance and voltage gain of LNA.

3.3 $\boldsymbol{V}$-$\boldsymbol{I}$ converter

Due to the relatively low driving capability, the output voltage from LNA is converted to current and drives the mixer. $V$-$I$ converter is used to convert output voltage of LNA to current. To save the DC consumption, the $V$-$I$ converter also applies current-reuse technology. The circuit is shown in Fig. 5 (common voltage controller and bias are not shown).

The amplified signal from LNA is applied to the gate of MN1a and MN1b. The signal is further amplified, and AC coupled to the gate of MN2a and MN2b. Then, signal current is generated and can be applied to the mixer through a low-impedance input point. $C_{1}$ is 0.35 pF, which is enough to couple the signal voltage. $C_{2}$ is set to 1 pF, because MN1a and MN1b have larger $W/L$ ratios. $R_{1}$ and $R_{2}$ are chosen to be 1 k$\Omega$ and 450 $\Omega$ separately. Because this circuit is using current-reuse technology, the bias current is shared in MN1 and MN2; VMID must act like AC ground and maintains a constant bias condition. A feedback mechanism (not shown in Fig. 5) is used. The feedback system is continuously monitoring the VMID and comparing it to reference voltage. If there are discrepancies, the feedback system will adjust the bias voltage of MN1 to pull VMID back to reference voltage.

3.4 Mixer

An active double-balanced mixer is used in the front-end. Because the receiver uses low-IF structure, 1/$f$ noise is a major noise source to the receiver. Compared to NMOS transistor, PMOS transistor has lower 1/$f$ noise. So the mixer uses PMOS to do the signal multiplication and deliver the IF signal in current mode. Because the entire front-end layout should be a compact style, the whole signal chain cannot be arranged in a straight line, so long, folded signal lines are unavoidable. Because the current signal is more robust to crosstalk or noise, a current mode mixer is used in this design. The topology of the mixer is shown in Fig. 6.

MP2a, MP2b, MP2c and MP2d are mixing transistors. The LO is applied to the gate with about 200 mV amplitude, while RF signal is injected from two common source points through $C_{1}$ differently. To inject the signal from the source point can avoid headroom problems in low voltage design. The mixer is loaded by NMOS current mirrors. A common mode amplifier AMP senses the common voltage of the output IF signal and keeps it to VREF by adjusting the bias voltage of MP1a and MP1b. $C_{\rm c}$ is the common mode compensation capacitor, which can keep the common mode control loop stable.

3.5 TIA and output buffer

The IF current coming from the mixer should be converted to voltage signal for test or successive filters. A TIA is used to do the task. The TIA and the following output buffer are shown in Fig. 7.

The $R_{1}$ in TIA converts current to voltage; $C_{1}$ in parallel with $R_{1}$ can provide first order filtering function. The cutoff frequency is set to 500 kHz.

The core amplifier used in TIA is shown in Fig. 8. It is a two stage full differential amplifier. The frequency extending technology from Ref. [7] is used to achieve more bandwidth with limited power consumption. The simulation shows, with a 1 pF capacitive loading, the amplifier still maintains 40 dB gain at 1.9 MHz with only 200 $\mu$A DC current. The buffer is similar to the core amplifier of TIA, but uses more current to drive an off-chip measuring apparatus.

3.6 Implementation and die photo

Based on the proposed wideband LNA and corresponding circuit, the front-end circuit test chip was fabricated in RF CMOS 0.18 $\mu$m process. The chip is mounted to the test board by COB method. The die photo is shown in Fig. 9. The receiver circuit occupies a silicon area of 520 $\times$ 220 $\mu$m$^2$. The remaining parts of the silicon area are filled with dummy metals and decoupling MOS capacitors. These MOS capacitors are connected between power and ground. Their existence will not affect the circuit performance notably.

4. Measurement results

The input impedance is wideband matched differentially over the whole operation bands, but without a balun which can work over such a wide band, the external SMD LC balun shown in Fig. 10 is used. When matched to differential impedance of 50 $\Omega$, the balun brings a loss of about 0.5 dB at the center frequency. This loss is added to the whole NF directly. This type of balun can provide about 100 MHz bandwidth, enough for 433/915 MHz band test. Figures 11 and 12 are $S_{11}$ parameters in 433 MHz and 915 MHz respectively.

Since the TIA of the front-end is designed to drive internal nodes, an external driver is needed to drive measurement instruments, and besides, a differential to single ended transformation is also needed. The onboard driver used for the test is shown in Fig. 13, the core operational amplifier is OPA356 from TI, which has a GBW of 200 MHz.

The linearity is tested through two-tone method. The space between two test tones is 100 kHz (Fig. 14). The measured input referenced IP3 point is shown in Fig. 15. The IIP3 point at 915 MHz is larger than one in 433 MHz. It is mainly caused by gain degradation of LNA in 915 MHz.

Due to the lack of a noise measurement instrument under 10 MHz, the noise measurement is accomplished with gain method. An additional preamplifier with 28 dB gain and 2.8 dB noise figure is used to overcome the noise floor of the spectrum analyzer. The noise figure of the front-end can be calculated by Eq. (12).

$$\begin{equation} \label{eq12} {\rm NF}=P_{\rm NOUTD} +174\, {\rm dBm/Hz-Gain}. \end{equation}$$

(12)

In Eq. (12), $P_{\rm NOUTD}$ denotes the power spectrum density when front-end input is terminated by a 50 $\Omega$ resistor, and gain is the total gain of the front-end plus the gain of preamplifier. The measured DSB NF at 424 kHz is about 9.7.

DC consumption of the receiver is measured by a multimeter; the proportions of current used by each module are shown in Fig. 16. Excluding test buffer, the total DC current of the front-end is only 1.44 mA.

5. Conclusion

A wideband RF front-end with current-reuse LNA has been presented in this paper. The measurement results show return loss, NF, linearity performance of the front-end. The RF front-end can operate at 433/915 MHz properly and achieves a performance suitable for SRD devices, its low current, small area characteristics especially will cut down the cost considerably.