1. Introduction

To avoid the loss caused by electro-static discharge (ESD), a good on-chip protection circuit is necessary. The output pad can be self-protected if its width is very large. However, in practice, the width is not generally enough. In particular, in the advanced process, the MOSFET is not robust enough because of its inhomogeneous turning-on characteristic^{[1, 2]}. Thus, it needs additional ESD protection devices, which may take up a lot of space. In addition, the triggering competition between the output transistor and the ESD protection device makes the design of the ESD difficult.

The robustness of the ESD can be improved using various layout techniques^[3], but theoretically the MOSFET is not a highly robust structure compared with SCR. Besides, the large parasitic capacitance is also a limitation for application.

In addition, a protection device triggered only by avalanche breakdown is not enough for the deep-submicron process because the inner circuit is highly vulnerable to ESD stress^[4].

A diode and power clamp in series structure is a good choice to reduce the occupied area^[4]. In the structure, $V_{\rm DD}$ and $V_{\rm SS}$ are protected by the robust power clamp device, and the output pad is connected to $V_{\rm DD}$ and $V_{\rm SS}$ rails through diodes respectively. The ESD stress at the output pad can apply to the power rails through the forward-biased diode and discharge through the power clamp. The voltage drop on the chip is then $V_{\rm PowerClamp}+V_{\rm diode}$. Besides, the parasitic resistance in the power rail cannot be ignored if their distance is very long. A higher clamp voltage means higher power dissipation, which is not beneficial for the protected output MOSFET.

2. Proposed structure

To minimize the occupied area and achieve high ESD robustness at the same time, an embedded output transistor with a novel structure is proposed. Its two-finger structure is shown in Fig. 1. The novel structure is composed of two complementary devices, device A (shown in Fig. 1(a)) and device B (shown in Fig. 1(b)). Both devices are symmetrical for isolation.

In device A, the output PMOS and power clamp GGNMOS (gate-grounded NMOS) are combined. In normal circuit operation, the Nwell in the output PMOS is biased to $V_{\rm DD}$ and surrounded by N$^+$. The output PMOS can be switched on and off as the conventional output transistor.

Under PS mode ESD stress (the output is positively stressed versus $V_{\rm SS}$), device A is equivalent to an SCR composed of Q1 and Q2, as shown by the line 1 in Fig. 2. Like the conventional LVTSCR (low-voltage-triggered SCR)^[5], this SCR can be triggered by the avalanche breakdown current in the embedded GGNMOS. For the conventional LVTSCR, if we neglect the small amplification effect before the device is turned on, the trigger criterion is

$\begin{equation} I_{\rm ava\_Q1} R_{\rm Pwell}>0.7\, {\rm V}. \end{equation}$

(1)

This means that the device can be triggered when the parasitic NPN B-E junction in NMOS is forward-biased by the avalanche current $I_{\rm ava\_Q1}$ and the resistance $R_{\rm Pwell}$. Besides, device A can also be triggered by the charging current in the parasitic capacitor $C$ between $V_{\rm DD}$ and $V_{\rm SS}$. Under PS mode stress, the potential of the floating $V_{\rm DD}$ is coupled to $V_{\rm SS}$. Thus, this capacitor can be charged through the forward-biased E-B junction in Q2, and then Q2 turns on. The trigger criterion is

$\begin{equation} (I_{\rm B\_Q2} \beta_{\rm Q2} M_{\rm Q1}+I_{\rm ava\_Q1}) R_{\rm Pwell} > 0.7 \, {\rm V}, \end{equation}$

(2)

where $I_{\rm B\_Q2}$ is the capacitor charging current, which is $C$d$V_{\rm DD}$/ d$t$. In a large-sized circuit, this parasitic capacitance can be larger than 10 nF^[6]. The rising time of ESD is less than 10 ns, therefore, a larger parasitic capacitance can lead to a lower trigger voltage, which is beneficial in protecting the output transistor.

In device A, both the electron and hole can be injected from the cathode and anode, whereas the hole current must be avalanche-generated in GGNMOS. Thus, the power dissipation of the SCR is much lower than GGNMOS and the $I_{\rm t2}$ is higher.

Under PD mode stress (the output is positively stressed versus $V_{\rm DD}$), the ESD current can discharge through the forward-biased E-B junction in Q2, as shown by the line 2 in Fig. 2.

In the same way, device B can protect the output transistors against the ND mode (the output is negatively stressed versus $V_{\rm DD}$) and the NS mode (the output is negatively stressed versus $V_{\rm SS}$) stress.

Besides, as shown by the line 3 in Fig. 2, the embedded GGNMOS in device A and GDPMOS (gate-$V_{\rm DD}$ PMOS) in device B can protect the power rails, even though their ESD robustness is not very high, as mentioned above. Considering that the GGNMOS or GDPMOS is part of the output protection structure, this power clamp is realized at the cost of almost no extra area. The ESD robustness can also be improved by a resistor connected to the gate or by the triggering circuit techniques^[7-9].

In addition, these power clamp devices exist in every output pad instead of only at the $V_{\rm DD}$ and $V_{\rm SS}$ pads in the conventional circuit floorplan. In the conventional circuit floorplan, the power clamp may be far away from the pad suffering ESD. However, for the proposed structure, if a pad suffers ESD stress, then the GGNMOS and GDPMOS in the neighboring pads can also quickly help it to discharge more ESD current, as shown in Fig. 3. The parasitic resistance in the power rails in the conventional layout can be neglected.

3. Test results

We fabricated the proposed structure and the conventional GGNMOS/GDPMOS structure in a 130 nm 1.2 V process. The widths of the novel structure and conventional GGNMOS/GDPMOS structure are 25 $\mu$m $\times$ 2 and 25 $\mu$m $\times$ 4, respectively. Their layouts are depicted in Fig. 4, and they are tested using a TLP (transmission line pulse) system to evaluate their ESD robustness.

Figure 5 shows the TLP $I$-$V$ curves (absolute value) of device A under PS mode stress, device B under ND mode stress, and a two-finger conventional LVTSCR^[10] under PS mode stress. Figure 6 shows the TLP $I$-$V$ (absolute value) curves of the two-finger embedded GGNMOS in device A, the two-finger embedded GDPMOS in device B, the four-finger conventional GGNMOS, and the four-finger conventional GDPMOS. We define the device failure when the leakage current is larger than 1 $\mu$A. The characteristics are summarized in Table 1. In our discrete device test, the $V_{\rm t1}$ of devices A and B is 6.2 V and 7.3 V, respectively. This may be too high to protect the inner devices. In actual application, the $V_{\rm t1}$ would be much lower than our tests because the discrete device tests cannot illustrate the impact by the parasitic capacitance in the power rails. Besides, the $V_{\rm t1}$ of the embedded NMOS (PMOS) can also be lowered easily by adding a resistor between the gate and $V_{\rm SS}$ ($V_{\rm DD}$), or by adding a trigger circuit^[7-9]. The $I_{\rm t2}$ are 3.24 A for device A and 2.12 A for device B, which is about three times higher than the four-finger GGNMOS and GDPMOS, respectively. The $V_{\rm t1}$ and $V_{\rm h}$ of the LVTSCR are lower than devices A and B because the length can be shorter without the integrated output MOS device. Nevertheless, this is only an ESD protection device and cannot be used as the output transistor. Then, its area efficiency is lower than the proposed devices.

In Fig. 6, the robustness of NMOS and PMOS is not high, as mentioned above. Their robustness is proportional to their width because their $V_{\rm t2}$ are much higher than their $V_{\rm t1}$^[11]. Therefore, the conventional power clamps, GGNMOS and GDPMOS, can be replaced by the embedded MOS structure. Note that this power clamp is realized at the cost of almost no extra area.

4. Conclusion

An area-efficient ESD protection structure is proposed, which is composed of a pair of complementary devices. In the proposed structure, the output transistor and the power clamp are combined to form an SCR to achieve high ESD robustness. This can be triggered not only by the avalanche current in the embedded MOSFET, but also by the parasitic capacitance charging current. In almost the same die area condition, the $I_{\rm t2}$ of the devices are 3.24 A and 2.12 A, respectively, which is nearly three times as high as the GGNMOS and GDPMOS structure. Besides, they can also provide 0.62 A and 0.35 A power clamp robustness, respectively. Thus, in practical terms, considering the additional current paths in the neighboring output pads, the robustness of the output may be higher, which is our future work.

Acknowledgments: The authors would like to thank the National Chiao-Tung University, Taiwan, China, for providing the measuring instruments.