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J. Semicond. > 2013, Volume 34 > Issue 11 > 114016

SEMICONDUCTOR DEVICES

A novel ESD protection structure for output pads

Hang Fan, Lingli Jiang and Bo Zhang

+ Author Affiliations

 Corresponding author: Fan Hang, fanmes@163.com

DOI: 10.1088/1674-4926/34/11/114016

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Abstract: Electro-static discharge (ESD) is always a serious threat to integrated circuits. To achieve higher robustness and a smaller die area at the same time, a novel protection structure for the output pad is proposed. The complementary SCR devices in this structure can protect not only the output under positive or negative stresses versus VDD or VSS, respectively, but also the power rails at the cost of almost no extra area. The robustness of the proposed structure is about three times higher than the conventional four-finger GGNMOS/GDPMOS structure in the same area condition.

Key words: electro-static dischargepower clampsilicon controlled rectifier

To avoid the loss caused by electro-static discharge (ESD), a good on-chip protection circuit is necessary. The output pad can be self-protected if its width is very large. However, in practice, the width is not generally enough. In particular, in the advanced process, the MOSFET is not robust enough because of its inhomogeneous turning-on characteristic[1, 2]. Thus, it needs additional ESD protection devices, which may take up a lot of space. In addition, the triggering competition between the output transistor and the ESD protection device makes the design of the ESD difficult.

The robustness of the ESD can be improved using various layout techniques[3], but theoretically the MOSFET is not a highly robust structure compared with SCR. Besides, the large parasitic capacitance is also a limitation for application.

In addition, a protection device triggered only by avalanche breakdown is not enough for the deep-submicron process because the inner circuit is highly vulnerable to ESD stress[4].

A diode and power clamp in series structure is a good choice to reduce the occupied area[4]. In the structure, VDD and VSS are protected by the robust power clamp device, and the output pad is connected to VDD and VSS rails through diodes respectively. The ESD stress at the output pad can apply to the power rails through the forward-biased diode and discharge through the power clamp. The voltage drop on the chip is then VPowerClamp+Vdiode. Besides, the parasitic resistance in the power rail cannot be ignored if their distance is very long. A higher clamp voltage means higher power dissipation, which is not beneficial for the protected output MOSFET.

To minimize the occupied area and achieve high ESD robustness at the same time, an embedded output transistor with a novel structure is proposed. Its two-finger structure is shown in Fig. 1. The novel structure is composed of two complementary devices, device A (shown in Fig. 1(a)) and device B (shown in Fig. 1(b)). Both devices are symmetrical for isolation.

Figure  1.  The proposed structure composed of (a) device A, and (b) device B.

In device A, the output PMOS and power clamp GGNMOS (gate-grounded NMOS) are combined. In normal circuit operation, the Nwell in the output PMOS is biased to VDD and surrounded by N+. The output PMOS can be switched on and off as the conventional output transistor.

Under PS mode ESD stress (the output is positively stressed versus VSS), device A is equivalent to an SCR composed of Q1 and Q2, as shown by the line 1 in Fig. 2. Like the conventional LVTSCR (low-voltage-triggered SCR)[5], this SCR can be triggered by the avalanche breakdown current in the embedded GGNMOS. For the conventional LVTSCR, if we neglect the small amplification effect before the device is turned on, the trigger criterion is

Iava_Q1RPwell>0.7V.

(1)
Figure  2.  The equivalent circuit of device A under ESD stress from the PS, PD and DS modes.

This means that the device can be triggered when the parasitic NPN B-E junction in NMOS is forward-biased by the avalanche current Iava_Q1 and the resistance RPwell. Besides, device A can also be triggered by the charging current in the parasitic capacitor C between VDD and VSS. Under PS mode stress, the potential of the floating VDD is coupled to VSS. Thus, this capacitor can be charged through the forward-biased E-B junction in Q2, and then Q2 turns on. The trigger criterion is

(IB_Q2βQ2MQ1+Iava_Q1)RPwell>0.7V,

(2)

where IB_Q2 is the capacitor charging current, which is CdVDD/ dt. In a large-sized circuit, this parasitic capacitance can be larger than 10 nF[6]. The rising time of ESD is less than 10 ns, therefore, a larger parasitic capacitance can lead to a lower trigger voltage, which is beneficial in protecting the output transistor.

In device A, both the electron and hole can be injected from the cathode and anode, whereas the hole current must be avalanche-generated in GGNMOS. Thus, the power dissipation of the SCR is much lower than GGNMOS and the It2 is higher.

Under PD mode stress (the output is positively stressed versus VDD), the ESD current can discharge through the forward-biased E-B junction in Q2, as shown by the line 2 in Fig. 2.

In the same way, device B can protect the output transistors against the ND mode (the output is negatively stressed versus VDD) and the NS mode (the output is negatively stressed versus VSS) stress.

Besides, as shown by the line 3 in Fig. 2, the embedded GGNMOS in device A and GDPMOS (gate-VDD PMOS) in device B can protect the power rails, even though their ESD robustness is not very high, as mentioned above. Considering that the GGNMOS or GDPMOS is part of the output protection structure, this power clamp is realized at the cost of almost no extra area. The ESD robustness can also be improved by a resistor connected to the gate or by the triggering circuit techniques[7-9].

In addition, these power clamp devices exist in every output pad instead of only at the VDD and VSS pads in the conventional circuit floorplan. In the conventional circuit floorplan, the power clamp may be far away from the pad suffering ESD. However, for the proposed structure, if a pad suffers ESD stress, then the GGNMOS and GDPMOS in the neighboring pads can also quickly help it to discharge more ESD current, as shown in Fig. 3. The parasitic resistance in the power rails in the conventional layout can be neglected.

Figure  3.  The additional discharge path through the protection devices at neighboring pads.

We fabricated the proposed structure and the conventional GGNMOS/GDPMOS structure in a 130 nm 1.2 V process. The widths of the novel structure and conventional GGNMOS/GDPMOS structure are 25 μm × 2 and 25 μm × 4, respectively. Their layouts are depicted in Fig. 4, and they are tested using a TLP (transmission line pulse) system to evaluate their ESD robustness.

Figure  4.  The layouts of (a) GGNMOS and (b) device A.

Figure 5 shows the TLP I-V curves (absolute value) of device A under PS mode stress, device B under ND mode stress, and a two-finger conventional LVTSCR[10] under PS mode stress. Figure 6 shows the TLP I-V (absolute value) curves of the two-finger embedded GGNMOS in device A, the two-finger embedded GDPMOS in device B, the four-finger conventional GGNMOS, and the four-finger conventional GDPMOS. We define the device failure when the leakage current is larger than 1 μA. The characteristics are summarized in Table 1. In our discrete device test, the Vt1 of devices A and B is 6.2 V and 7.3 V, respectively. This may be too high to protect the inner devices. In actual application, the Vt1 would be much lower than our tests because the discrete device tests cannot illustrate the impact by the parasitic capacitance in the power rails. Besides, the Vt1 of the embedded NMOS (PMOS) can also be lowered easily by adding a resistor between the gate and VSS (VDD), or by adding a trigger circuit[7-9]. The It2 are 3.24 A for device A and 2.12 A for device B, which is about three times higher than the four-finger GGNMOS and GDPMOS, respectively. The Vt1 and Vh of the LVTSCR are lower than devices A and B because the length can be shorter without the integrated output MOS device. Nevertheless, this is only an ESD protection device and cannot be used as the output transistor. Then, its area efficiency is lower than the proposed devices.

Figure  5.  The TLP I-V curves of devices A and B.
Table  1.  The ESD characteristics of devices A, B and the conventional MOSFET.
DownLoad: CSV  | Show Table

In Fig. 6, the robustness of NMOS and PMOS is not high, as mentioned above. Their robustness is proportional to their width because their Vt2 are much higher than their Vt1[11]. Therefore, the conventional power clamps, GGNMOS and GDPMOS, can be replaced by the embedded MOS structure. Note that this power clamp is realized at the cost of almost no extra area.

Figure  6.  The TLP I-V curves of the two-finger embedded MOSFET and the four-finger conventional GGNMOS/GDPMOS structure.

An area-efficient ESD protection structure is proposed, which is composed of a pair of complementary devices. In the proposed structure, the output transistor and the power clamp are combined to form an SCR to achieve high ESD robustness. This can be triggered not only by the avalanche current in the embedded MOSFET, but also by the parasitic capacitance charging current. In almost the same die area condition, the It2 of the devices are 3.24 A and 2.12 A, respectively, which is nearly three times as high as the GGNMOS and GDPMOS structure. Besides, they can also provide 0.62 A and 0.35 A power clamp robustness, respectively. Thus, in practical terms, considering the additional current paths in the neighboring output pads, the robustness of the output may be higher, which is our future work.

Acknowledgments: The authors would like to thank the National Chiao-Tung University, Taiwan, China, for providing the measuring instruments.


[1]
Song B, Han Y, Li M, et al. Substrate-triggered GGNMOS in 65 nm CMOS process for ESD application. Electron Lett, 2010, 46(7):518 doi: 10.1049/el.2010.0205
[2]
Lee J H, Shih J R, Yang D H, et al. A simple solution for low-driving-current output buffer failed at the low voltage ESD zapping event. International Symp Physical and Failure Analysis of Integrated Circuits (IPFA), 2012 http://ieeexplore.ieee.org/document/6306259/authors
[3]
Ker M D, Chen W Y, Shieh W T, et al. New ballasting layout schemes to improve ESD robustness of I/O buffers in fully silicided CMOS process. Symp EOS/ESD Symposium, 2009:1 http://ieeexplore.ieee.org/document/5299049/keywords
[4]
Yeh C T, Ker M D. Capacitor-less design of power-rail ESD clamp circuit with adjustable holding voltage for on-chip ESD protection. IEEE J Solid-State Circuits, 2010, 45(11):2476 https://www.infona.pl/resource/bwmeta1.element.ieee-art-000005597958
[5]
Amerasekera A, Duvvury C. ESD in silicon integrated circuits. 2nd ed. England:John Wiley & Sons, Ltd., 2002:150
[6]
Amerasekera A, Duvvury C. ESD in silicon integrated circuits. 2nd ed. England:John Wiley & Sons, Ltd., 2002:256
[7]
Chen T Y, Ker M D. Investigation of the gate-driven effect and substrate-triggered effect on ESD robustness of CMOS devices. IEEE Trans Device Mater Reliab, 2001, 1(4):190 doi: 10.1109/7298.995833
[8]
Wang G C, Chen C H, Huang W H, et al. Gate-driven 3.3 V ESD clamp using 1.8 V transistors. International Conf IC Design & Technology (ICICDT), 2011
[9]
Wang C T, Ker M D. Design of 2×VDD-tolerant power-rail ESD clamp circuit with consideration of gate leakage current in 65-nm CMOS technology. Electron Devices, 2010, 57(6):1460 doi: 10.1109/TED.2010.2046457
[10]
Amerasekera A, Duvvury C. ESD in silicon integrated circuits. 2nd ed. England:John Wiley & Sons, Ltd., 2002:98
[11]
Ker M D, Chen J H. Self-substrate-triggered technique to enhance turn-on uniformity of multi-finger ESD protection devices. IEEE J Solid-State Circuits, 2006, 41:2601 doi: 10.1109/JSSC.2006.883331
Fig. 1.  The proposed structure composed of (a) device A, and (b) device B.

Fig. 2.  The equivalent circuit of device A under ESD stress from the PS, PD and DS modes.

Fig. 3.  The additional discharge path through the protection devices at neighboring pads.

Fig. 4.  The layouts of (a) GGNMOS and (b) device A.

Fig. 5.  The TLP I-V curves of devices A and B.

Fig. 6.  The TLP I-V curves of the two-finger embedded MOSFET and the four-finger conventional GGNMOS/GDPMOS structure.

Table 1.   The ESD characteristics of devices A, B and the conventional MOSFET.

[1]
Song B, Han Y, Li M, et al. Substrate-triggered GGNMOS in 65 nm CMOS process for ESD application. Electron Lett, 2010, 46(7):518 doi: 10.1049/el.2010.0205
[2]
Lee J H, Shih J R, Yang D H, et al. A simple solution for low-driving-current output buffer failed at the low voltage ESD zapping event. International Symp Physical and Failure Analysis of Integrated Circuits (IPFA), 2012 http://ieeexplore.ieee.org/document/6306259/authors
[3]
Ker M D, Chen W Y, Shieh W T, et al. New ballasting layout schemes to improve ESD robustness of I/O buffers in fully silicided CMOS process. Symp EOS/ESD Symposium, 2009:1 http://ieeexplore.ieee.org/document/5299049/keywords
[4]
Yeh C T, Ker M D. Capacitor-less design of power-rail ESD clamp circuit with adjustable holding voltage for on-chip ESD protection. IEEE J Solid-State Circuits, 2010, 45(11):2476 https://www.infona.pl/resource/bwmeta1.element.ieee-art-000005597958
[5]
Amerasekera A, Duvvury C. ESD in silicon integrated circuits. 2nd ed. England:John Wiley & Sons, Ltd., 2002:150
[6]
Amerasekera A, Duvvury C. ESD in silicon integrated circuits. 2nd ed. England:John Wiley & Sons, Ltd., 2002:256
[7]
Chen T Y, Ker M D. Investigation of the gate-driven effect and substrate-triggered effect on ESD robustness of CMOS devices. IEEE Trans Device Mater Reliab, 2001, 1(4):190 doi: 10.1109/7298.995833
[8]
Wang G C, Chen C H, Huang W H, et al. Gate-driven 3.3 V ESD clamp using 1.8 V transistors. International Conf IC Design & Technology (ICICDT), 2011
[9]
Wang C T, Ker M D. Design of 2×VDD-tolerant power-rail ESD clamp circuit with consideration of gate leakage current in 65-nm CMOS technology. Electron Devices, 2010, 57(6):1460 doi: 10.1109/TED.2010.2046457
[10]
Amerasekera A, Duvvury C. ESD in silicon integrated circuits. 2nd ed. England:John Wiley & Sons, Ltd., 2002:98
[11]
Ker M D, Chen J H. Self-substrate-triggered technique to enhance turn-on uniformity of multi-finger ESD protection devices. IEEE J Solid-State Circuits, 2006, 41:2601 doi: 10.1109/JSSC.2006.883331
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    Hang Fan, Lingli Jiang, Bo Zhang. A novel ESD protection structure for output pads[J]. Journal of Semiconductors, 2013, 34(11): 114016. doi: 10.1088/1674-4926/34/11/114016
    H Fan, L L Jiang, B Zhang. A novel ESD protection structure for output pads[J]. J. Semicond., 2013, 34(11): 114016. doi:  10.1088/1674-4926/34/11/114016.
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    Received: 01 April 2013 Revised: 16 May 2013 Online: Published: 01 November 2013

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      Hang Fan, Lingli Jiang, Bo Zhang. A novel ESD protection structure for output pads[J]. Journal of Semiconductors, 2013, 34(11): 114016. doi: 10.1088/1674-4926/34/11/114016 ****H Fan, L L Jiang, B Zhang. A novel ESD protection structure for output pads[J]. J. Semicond., 2013, 34(11): 114016. doi:  10.1088/1674-4926/34/11/114016.
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      Hang Fan, Lingli Jiang, Bo Zhang. A novel ESD protection structure for output pads[J]. Journal of Semiconductors, 2013, 34(11): 114016. doi: 10.1088/1674-4926/34/11/114016 ****
      H Fan, L L Jiang, B Zhang. A novel ESD protection structure for output pads[J]. J. Semicond., 2013, 34(11): 114016. doi:  10.1088/1674-4926/34/11/114016.

      A novel ESD protection structure for output pads

      DOI: 10.1088/1674-4926/34/11/114016
      Funds:

      the National Natural Science Foundation of China 61274027

      Project supported by the National Natural Science Foundation of China (No. 61274027)

      More Information
      • Corresponding author: Fan Hang, fanmes@163.com
      • Received Date: 2013-04-01
      • Revised Date: 2013-05-16
      • Published Date: 2013-11-01

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