Fig. 1.
Cross section of the LDMOS in a 0.35 $\mu $ m BCD process with a 3D diagram of the source region.
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| Citation: |
Lingli Jiang, Hang Fan, Lijuan Lin, Bo Zhang. ESD performance of LDMOS with source-bulk layout structure optimization[J]. Journal of Semiconductors, 2013, 34(12): 124003. doi: 10.1088/1674-4926/34/12/124003
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L L Jiang, H Fan, L J Lin, B Zhang. ESD performance of LDMOS with source-bulk layout structure optimization[J]. J. Semicond., 2013, 34(12): 124003. doi: 10.1088/1674-4926/34/12/124003.
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ESD performance of LDMOS with source-bulk layout structure optimization
DOI: 10.1088/1674-4926/34/12/124003
More Information
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Abstract
To enhance the robustness of LDMOS ESD protection devices, the influence of a source-bulk layout structure is analyzed by theoretical analysis and numerical simulation. Novel structures with varied source-bulk layout structures are fabricated and compared. As demonstrated by TLP testing, the optimized structure has an 88% larger It2 than a conventional one, and its Vt1 is reduced from 55.53 to 50.69 V.-
Keywords:
- ESD,
- LDMOS,
- source-bulk layout structure
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References
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