Fig. 1.
The block diagram of the proposed power-aware optical chip-to-chip transceiver design.
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Jamshid Sangirov, Ikechi Augustine Ukaegbu, Gulomjon Sangirov, Tae-Woo Lee, Hyo-Hoon Park. Power-aware transceiver design for half-duplex bidirectional chip-to-chip optical interconnects[J]. Journal of Semiconductors, 2013, 34(12): 125001. doi: 10.1088/1674-4926/34/12/125001
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J Sangirov, I A Ukaegbu, G Sangirov, T W Lee, H H Park. Power-aware transceiver design for half-duplex bidirectional chip-to-chip optical interconnects[J]. J. Semicond., 2013, 34(12): 125001. doi: 10.1088/1674-4926/34/12/125001.
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Power-aware transceiver design for half-duplex bidirectional chip-to-chip optical interconnects
DOI: 10.1088/1674-4926/34/12/125001
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Abstract
A power-aware transceiver for half-duplex bidirectional chip-to-chip optical interconnects has been designed and fabricated in a 0.13 μm complementary metal-oxide-semiconductor (CMOS) technology. The transceiver can detect the presence and absence of received signals and saves 55% power in Rx enabled mode and 45% in Tx enabled mode. The chip occupies an area of 1.034 mm2 and achieves a 3-dB bandwidth of 6 GHz and 7 GHz in Tx and Rx modes, respectively. The disabled outputs for the Tx and Rx modes are isolated with 180 dB and 139 dB, respectively, from the enabled outputs. Clear eye diagrams are obtained at 4.25 Gbps for both the Tx and Rx modes. -
References
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