An 8-bit 100-MS/s digital-to-skew converter embedded switch with a 200-ps range for time-interleaved sampling

Xiaoshi Zhu; Chixiao Chen; Jialiang Xu; Fan Ye; Junyan Ren

doi:10.1088/1674-4926/34/3/035003

J. Semicond. > 2013, Volume 34 > Issue 3 > 035003

SEMICONDUCTOR INTEGRATED CIRCUITS

An 8-bit 100-MS/s digital-to-skew converter embedded switch with a 200-ps range for time-interleaved sampling

Xiaoshi Zhu¹, Chixiao Chen¹, Jialiang Xu¹, Fan Ye^1, and Junyan Ren^{1, 2}

+ Author Affiliations

Corresponding author: Ye Fan, Email:fanye@fudan.edu.cn

DOI: 10.1088/1674-4926/34/3/035003

Abstract: A sampling switch with an embedded digital-to-skew converter (DSC) is presented. The proposed switch eliminates time-interleaved ADCs' skews by adjusting the boosted voltage. A similar bridged capacitors' charge sharing structure is used to minimize the area. The circuit is fabricated in a 0.18 μm CMOS process and achieves sub-1 ps resolution and 200 ps timing range at a rate of 100 MS/s. The power consumption is 430 μW at maximum. The measurement result also includes a 2-channel 14-bit 100 MS/s time-interleaved ADCs (TI-ADCs) with the proposed DSC switch's demonstration. This scheme is widely applicable for the clock skew and aperture error calibration demanded in TI-ADCs and SHA-less ADCs.

Key words: sample-time error, digital-to-skew converter, bootstrapped switch, calibration, time-interleaved

References

[1]	Straayer M, Perrott M. A multi-path gated ring oscillator TDC with first-order noise shaping. IEEE J Solid-State Circuits, 2009, 44(4):1089 doi: 10.1109/JSSC.2009.2014709
[2]	Yu B, Chen C, Zhu Y, et al. A 14-bit 200-ms/s time-interleaved ADC with sample-time error detection and cancelation. IEEE Asian Solid State Circuits Conference (A-SSCC), 2011:349 http://ieeexplore.ieee.org/document/6123586/
[3]	El-Chammas M, Murmann B. A 12-gs/s 81-mw 5-bit time-interleaved flash ADC with background timing skew calibration. IEEE J Solid-State Circuits, 2011, 46(4):838 doi: 10.1109/JSSC.2011.2108125
[4]	Agnes A, Bonizzoni E, Malcovati P, et al. A 9.4-ENOB 1 V 3.8μW 100 ks/s SAR ADC with time-domain comparator. Digest of Technical Papers, IEEE International Solid-State Circuits Conference, 2008:246 https://www.researchgate.net/publication/4332071_A_94-ENOB_1V_38mW_100kSs_SAR_ADC_with_Time-Domain_Comparator

Fig. 1. A simple circuit topology of conventional DSC.

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Fig. 2. Cascading of conventional DSC to expand dynamic range.

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Fig. 3. (a) Traditional bootstrapped switch. (b) Timing graph of the voltage dependent skew.

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Fig. 4. Proposed DSC embedded switch.

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Fig. 5. 8-bit charge-redistribution C-2C DAC with a unit scaling capacitor.

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Fig. 6. 8-bit 100-MS/s digital-to-skew converter die photograph.

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Fig. 7. Post simulation of the proposed circuits on (a) INL and (b) DNL.

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Fig. 8. Simulated delay line characteristic.

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Fig. 9. Measured de-skew function by the proposed DSC sampling switch. (a) Before calibration. (b) After calibration.

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[1]	Straayer M, Perrott M. A multi-path gated ring oscillator TDC with first-order noise shaping. IEEE J Solid-State Circuits, 2009, 44(4):1089 doi: 10.1109/JSSC.2009.2014709
[2]	Yu B, Chen C, Zhu Y, et al. A 14-bit 200-ms/s time-interleaved ADC with sample-time error detection and cancelation. IEEE Asian Solid State Circuits Conference (A-SSCC), 2011:349 http://ieeexplore.ieee.org/document/6123586/
[3]	El-Chammas M, Murmann B. A 12-gs/s 81-mw 5-bit time-interleaved flash ADC with background timing skew calibration. IEEE J Solid-State Circuits, 2011, 46(4):838 doi: 10.1109/JSSC.2011.2108125
[4]	Agnes A, Bonizzoni E, Malcovati P, et al. A 9.4-ENOB 1 V 3.8μW 100 ks/s SAR ADC with time-domain comparator. Digest of Technical Papers, IEEE International Solid-State Circuits Conference, 2008:246 https://www.researchgate.net/publication/4332071_A_94-ENOB_1V_38mW_100kSs_SAR_ADC_with_Time-Domain_Comparator

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Received: 16 May 2012 Revised: 20 October 2012 Online: Published: 01 March 2013

A sampling switch with an embedded digital-to-skew converter (DSC) is presented. The proposed switch eliminates time-interleaved ADCs' skews by adjusting the boosted voltage. A similar bridged capacitors' charge sharing structure is used to minimize the area. The circuit is fabricated in a 0.18 μm CMOS process and achieves sub-1 ps resolution and 200 ps timing range at a rate of 100 MS/s. The power consumption is 430 μW at maximum. The measurement result also includes a 2-channel 14-bit 100 MS/s time-interleaved ADCs (TI-ADCs) with the proposed DSC switch's demonstration. This scheme is widely applicable for the clock skew and aperture error calibration demanded in TI-ADCs and SHA-less ADCs.

An 8-bit 100-MS/s digital-to-skew converter embedded switch with a 200-ps range for time-interleaved sampling

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An 8-bit 100-MS/s digital-to-skew converter embedded switch with a 200-ps range for time-interleaved sampling

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An 8-bit 100-MS/s digital-to-skew converter embedded switch with a 200-ps range for time-interleaved sampling

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