Fig. 1.
Weight voltage type DAC idea diagram.
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| Citation: |
Qixing Chen, Qiyu Luo. The architecture design of a 2mW 18-bit high speed weight voltage type DAC based on dual weight resistance chain[J]. Journal of Semiconductors, 2013, 34(3): 035010. doi: 10.1088/1674-4926/34/3/035010
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Q X Chen, Q Y Luo. The architecture design of a 2mW 18-bit high speed weight voltage type DAC based on dual weight resistance chain[J]. J. Semicond., 2013, 34(3): 035010. doi: 10.1088/1674-4926/34/3/035010.
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The architecture design of a 2mW 18-bit high speed weight voltage type DAC based on dual weight resistance chain
DOI: 10.1088/1674-4926/34/3/035010
More Information
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Abstract
At present, the architecture of a digital-to-analog converter (DAC) in essence is based on the weight current, and the average value of its D/A signal current increases in geometric series according to its digital signal bits increase, which is 2n-1 times of its least weight current. But for a dual weight resistance chain type DAC, by using the weight voltage manner to D/A conversion, the D/A signal current is fixed to chain current Icha; it is only 1/2n-1 order of magnitude of the average signal current value of the weight current type DAC. Its principle is:n pairs dual weight resistances form a resistance chain, which ensures the constancy of the chain current; if digital signals control the total weight resistance from the output point to the zero potential point, that could directly control the total weight voltage of the output point, so that the digital signals directly turn into a sum of the weight voltage signals; thus the following goals are realized:(1) the total current is less than 200 μA; (2) the total power consumption is less than 2 mW; (3) an 18-bit conversion can be realized by adopting a multi-grade structure; (4) the chip area is one order of magnitude smaller than the subsection current-steering type DAC; (5) the error depends only on the error of the unit resistance, so it is smaller than the error of the subsection current-steering type DAC; (6) the conversion time is only one action time of switch on or off, so its speed is not lower than the present DAC.-
Keywords:
- DAC,
- weight resistance,
- dual resistance,
- resistance chain,
- weight voltage,
- weight current
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References
[1] Van de Plassche R J. Integrated analog-to-digital and digital-to-analog converters. Boston, MA, USA:Kluwer Academic Publishers, 1994[2] Razavi B. Principles of data conversion system design. New York:IEEE Press, 1995[3] Chen Qixing. SNR optimized replacement type A/D and D/A converter. SIPO of China, Invention Patent No. ZL 03124548X. Authorization published 2010.4.14[4] Chen Qixing, Luo Qiyu. Replacement type DAC/ADC and realizing method for logarithm compression ratio. Journal of Data Acquisition & Processing, 2007, (1):115 doi: 10.1088/1674-4926/34/3/035010/meta[5] Chen Qixing, Luo Qiyu, Chen Bin. Replacement type grading parallel method research on ultra-high speed AD converter. Computer and Information Technology, 2005-1[6] Luo Qiyu, Chen Bin, Chen Qixing. A weight voltage DAC been chained by weight resistance. Computer and Information Technology, 2011, 19(4):18 doi: 10.1088/1674-4926/34/3/035010/meta[7] Chen Qixing, Luo Qiyu. Weight voltage type ADC and DAC based on dual weight resistance chain. SIPO of China, Invention Patent, International Application No.:PCT/CN2012/000997, 2012.7.27[8] Allen P E, Holberg D R. CMOS analog circuit design. 2nd ed. Oxford University Press, Inc, 2002[9] Xu Bulu. Design and verification of a 10-bit 1.2-V 100-MSPS D/A IP core based on a 0.13-μm low power CMOS process. Journal of Semiconductors, 2010, 31(9):095007 http://www.jos.ac.cn/bdtxbcn/ch/reader/view_abstract.aspx?file_no=10011502&flag=1 -
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